Author Topic: Just another DC Load  (Read 3713 times)

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Offline henmillTopic starter

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Just another DC Load
« on: January 24, 2025, 06:06:12 am »
To quote Dave: "Hi!"

I've been working on a DIY DC Load for m'lab. It started as most DIY DC Loads start I imagine: because you need a frickin adjustable load to test something! In my case, a silly mod to 15V power supply.

The goal was to first and foremost use stuff I have on hand or could have for cheap/free. So I ended up up-cycling a couple heatsinks and using a small 2U server PC case I have. It has been sitting unused for at least 3 years so I figured why not. I also happened to have an old ATX power supply that was hacked up and used briefly as my bench 5V and 12V supply. [Light bulbs coming on everywhere]

Originally I wanted to put it in a spiffy extruded case like one of those automotive inverters, but couldn't find a free one fast enough. But the PC case is pretty cool I think, albeit big. With all the space, it might eventually morph into a horribly hacked semblance of an SMU one day....

The performance goal was to be able to sink at least 50W at up to 24V. The 2nd proto (probably temporary final version) is able to do that pretty easily.

I went through an early proto stage with some random IRF FETs I had access to just to prove out the control board. Then I weighed my options between buying a few cheapish power FETs, without SOA for DC, maybe designing a PCB, or just doing it right by starting with an IXYS Linear FET. So I paid a little under 9 American Dollarbucks for a IXTH80N075L2, just so I could go full overkill and feel safe about not blowing this thing up (easily).

So here's the rundown of the design, and I'd love any input on what I should add, such as protections, improvements etc.

DCin --> Power Resistor (2 or 4 ohms) --> IXYS Linear Fet --> 100mR Sense Res -- GND
Quad op amp to buffer control input from 10-turn Pot, scale it down by 10, drive powerFEt, provide scaled Vout to panel meter
Up-cycled PC heatsinks for the FET and power resistors
Amazonian banana binding posts and power resistors. Have 5x 4R 100W resistors. Considering 2S-2P configuration if I can find the right heatsink

You can see all the pictures here: https://imgur.com/a/dc-load-linear-power-mod-xqmjoMd

Having trouble attaching more than one pic due to file size? Gotta get to bed but will direct upload more pics later.

Cheers!


« Last Edit: January 24, 2025, 06:12:17 am by henmill »
 

Offline drksy

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Re: Just another DC Load
« Reply #1 on: January 24, 2025, 07:05:54 am »
-why are you buffering Vpot twice?
-u4 needs compensation, otherwise this is just an oscillator. You need some 100p - 10n ceramic cap from u4_in_- to u4_output, remove the wire from u4_in_- to r_sense_+, and add a resistor instead (~10k - 100k) between u4_in_- and r_sense_+. With LMC648 probably 10k and 1n are sensible.
-what are those r_power resistors above the mosfet doing?
-you need some bulk decoupling for vcc, ~100u electrolytic in addition to some other ceramic caps in parallel, 1u + 100n + 10n, 10n as close to u4_vcc as possible.
-that 3d printed plastic clamp might melt and stink when you heat up the mosfet with a significant load. I would use some metal holder/screws instead.

Give this video a watch https://www.youtube.com/watch?v=vd5IBFFjnOc, shows how it's done (see pic for schematic)

overall: jank/10  :-+ But keep improving
« Last Edit: January 24, 2025, 07:41:56 am by drksy »
 

Offline MarkF

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Offline henmillTopic starter

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Re: Just another DC Load
« Reply #3 on: January 24, 2025, 04:23:05 pm »
Hi drksy, thanks for the feedback. I'll address your comments point-by-point:

- buffering Vpot twice: Well no good reason really, I think I did it because I was changing up the configuration and it was convenient, and I thought this was a good way to use one of the unused opamps instead of terminating it. I realize this multiplies any offset error but in this case it doesn't matter too much as it is just the reference voltage. (sorry for providing a not 100% accurate schematic of what is implemented on the protoboard)

- u4 compensation: I actually do have a cap across the output to -input. I think I used a 47pF.. You might be able to point it out if you look at the close up of the PCB in the attached image.
  And thanks for the recommendation on the connection to the sense node. I thought maybe no series resistance was necessary given the very high input impedance of the op amp. Is the Res/cap combo mostly to act as low pass filter?

- power resistors: They are there to share the overall power dissipation. Probably not necessary I guess with my awesome Linear FET. Just wanted some kind of overall current limiting in case I do something stupid (high probability)

- bulk decoupling: I have a 10uF on the board where 12V comes in, and you can't see it but there is a 100nF underneath the board as close to VCC pin as possible.

- 3d printed clamp: yes I realize this is a sh*t solution for mounting. I have some PET material I may use to make a new holder that can withstand a bit higher temp. The hope is my heatsinking will be so good that the plastic will not get very warm. I tried and failed to tap the copper heatsink.

I will keep looking for a more appropriate heatsink so I can mount the FET vertically and solder into a PCB. But for now I'm pretty pleased with the performance!

Thanks again for the comments! :)

EDIT: I need to correct my statement about u4 compensation. I had a feedback cap for the amp driving the scaled current monitor amp, NOT the amp driving the mosfet. I am still working out the value for feedback cap as of 1/27, but am learning a lot and having fun


« Last Edit: January 28, 2025, 04:35:24 am by henmill »
 

Offline Kleinstein

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Re: Just another DC Load
« Reply #4 on: January 24, 2025, 05:44:23 pm »
The series resistor in the feedback is needed to make the capacitor work. It is the RC combination that matter. The shunt resistor is pretty low to start with. So the extra resistor is really needed to get good stability.

Another small point would be to have some RC combination across the FET from drain to source (e.g. some 100 nF and 100 ohms - I don't remember to best values). This would help against oscillation / ringing with a difficult load with a lot of low loss inductance.

The extra resistors are OK as a last line of defense (e.g. also with reversed polarity be acident). This is actually a good idea to have it.
Another way in this direction could be a fuse.
 

Offline henmillTopic starter

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Re: Just another DC Load
« Reply #5 on: January 24, 2025, 06:15:26 pm »
Kleinstein: "when you say the resistor in the feedback is needed to make the capacitor work", you are just referring to the cap from output to -input right? We are not suggesting a cap to Gnd at the -input right? I think I know the answer because adding capacitance to the inverting terminal is generally a very bad idea right?

About the idea to have RC across the FET drain to source, are you suggesting like an RC snubber? Cap in series with resistor? I could implement that, sure. Would an example where this is useful be like if I'm loading a switching regulator?

About fusing/protection, probably a good idea to have one, I'll add that to the list. But I am also thinking I could free up one of the opamps and use it like a comparator for overcurrent protection. I have some pretty beefy solid state relays (also from IXYS coincidentally) that I'm thinking to use for a means to disconnect the load.

Here's a crude schematic of what I think are the suggestions:2488463-0
 

Offline Kleinstein

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Re: Just another DC Load
« Reply #6 on: January 24, 2025, 10:44:11 pm »
The drawing is Ok. The resistor in front of the gater is normally choosen smaller, more like 50 or 100 ohms so that the OP-amps is OK with driving this resistance together with the gate capacitance.
For suitable values for the snubbers I would run the circuit through a simulation, e.g. with LTspice. Chances are the values are not that critical, though it can make a difference when testing a lab supply with the load. Some lab supply circuits can have an ouput impedance that look similar to an near ideal inductor and wihout the snubber the electronic load may oscillate with such a load, even with the compensation around the OP-amp.

If paranoid about the load, there is one more case: when the load is activated before the DUT / supply is connected the OP-amp will turn on the FET all the way and take some time to start regulating. This means there could be a large initial current pulse, that could be an issue. At least one could limit the maximum gate voltage. Ideally one would check the drain voltage and limit the control when the drain voltage is too low. This could be something in the direction of a minimal resistance for the simulated mode that is somewhat larger than the shunt plus FET R_on.
 

Online temperance

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Re: Just another DC Load
« Reply #7 on: January 24, 2025, 11:08:53 pm »
The only correct load is this one:
https://www.eevblog.com/forum/projects/dynamic-electronic-load-project/

The stability analysis can be found in the thread. You will need R9 and C4 for stability otherwise the MOSFET and the wiring going to the drain will form an oscillator on itself. With on itself I mean that the servo amp is not involved and compensating the servo amp doesn't help anything.

All the others including the one presented in the YT video are brilliant oscillators. Specially those with 10 K gate resistors or those using op amps with large open loop output resistance. They don't. I made simplified analysis in an other thread long ago. But it is unpleasant reading because the Dummy load crowd came to piss on me stating I'm wrong. A proof of what I stated is being presented with real hardware quickly put together to prove my point. Oscilloscope screenshots are included.

Edit: repaired my grammar.
« Last Edit: January 25, 2025, 04:34:32 pm by temperance »
 
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Offline drksy

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Re: Just another DC Load
« Reply #8 on: January 25, 2025, 08:07:34 am »
The only correct load is this one:
https://www.eevblog.com/forum/projects/dynamic-electronic-load-project/

that's a pretty good design with a thorough AC analysis. I would follow that to the T, using precisely the same component values and the opamp itself. LT1013 is an excellent opamp and a much better one than OP had originally chosen for this job.

It would make for a very reliable PSU tester for transient response and such. For a more general purpose electronic load, I would be looking for features like constant-power, constant-resistance, four-wire sensing, input protections like reverse current and reverse polarity, and some software that makes it useful for battery discharge/cutoff, component characterization, etc. But then you have to draw the DIY line somewhere! With that 300Hz oscillator baked in, it seems this was purpose-built to be a fast step load.

From a learning/fun perspective, this can be a rewarding project, but really, hard to beat the 30 dollar electronic loads you find on Aliexpress that are much more useful as a general-purpose tool.
 

Online temperance

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Re: Just another DC Load
« Reply #9 on: January 25, 2025, 04:29:37 pm »
Quote
From a learning/fun perspective, this can be a rewarding project, but really, hard to beat the 30 dollar electronic loads you find on Aliexpress that are much more useful as a general-purpose tool.

Those $30 dummy loads are all faulty and just like many schematics found on the web very good oscillators. (Like 1...10 K gate resistors and a poor attempt at compensating the op amp which is nearly impossible with the high gate drive resistance unless you prefer a sloppy response in the ms range.)

Save yourself the trouble and buy the components shown in the Thread by Jay_Diddy_B. They don't cost that much. (Including the IRF520. Don't swap this with anything else unless you understand the requirements)
« Last Edit: January 25, 2025, 04:35:27 pm by temperance »
 

Offline henmillTopic starter

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Re: Just another DC Load
« Reply #10 on: January 27, 2025, 05:18:04 am »
The drawing is Ok. The resistor in front of the gater is normally choosen smaller, more like 50 or 100 ohms so that the OP-amps is OK with driving this resistance together with the gate capacitance.
For suitable values for the snubbers I would run the circuit through a simulation, e.g. with LTspice. Chances are the values are not that critical, though it can make a difference when testing a lab supply with the load. Some lab supply circuits can have an ouput impedance that look similar to an near ideal inductor and wihout the snubber the electronic load may oscillate with such a load, even with the compensation around the OP-amp.

If paranoid about the load, there is one more case: when the load is activated before the DUT / supply is connected the OP-amp will turn on the FET all the way and take some time to start regulating. This means there could be a large initial current pulse, that could be an issue. At least one could limit the maximum gate voltage. Ideally one would check the drain voltage and limit the control when the drain voltage is too low. This could be something in the direction of a minimal resistance for the simulated mode that is somewhat larger than the shunt plus FET R_on.

To your first point about gate R, understood, I have been playing with some simulations and 100R seems like a good value in most cases. However, this is with a FET that is different than what I am using. So I need to follow some of what is described in Jay_Diddy_B's (JDB) thread because he goes through setting up a model for a specific part (i.e., to get the gate capacitances right).

About the snubber, I have a bunch of 1R 3W resistors, and options for 1uF and 2.2uF ceramic caps, so will make a snubber, probably either 1R or 2R with the cap.

To your point about brief inrush/overshoot you might call it, I have wondered about that. With gate voltage maxed on a 12V system, the FET could allow a pretty large current momentarily. I think the series Limit resistors help with that, both in terms of limiting the current and sharing power dissipation. I'm trying to think of ways to clamp the gate voltage precisely to a value that is above my expected needed value, and is done easily with the parts I have haha.

@temperance: Thank you for linking that thread, it is so valuable. I have downloaded the spice files and have been playing around both in LTSpice and TI's TINA software. The TINA software is nice because you can really quickly and easily generate plots of Gain and Phase, and calculate phase margin. But I'm not sure it is doing the same thing as the LTSpice version... and I don't have a clear example of how to setup a model for my FET like JDB shows in the post you linked. So I think I'll try to mimic the analysis in LTSpice, but TINA has been quite useful for iterating with different component values as the sim runs quite fast.

Not sure if you caught the details in my first description, but I have a chosen FET that I splurged on and do not plan to deviate from (unless I blow it up). I also want to continue to use my opamp, LMC6484, as it is plenty capable, even though I originally bought it for other reasons (ultra low leakage measurement type stuff).

So now the task is to get the simulation as true-to-life as I can, and update component values around that. I think I'll start on a better PCB/mounting solution but for the immediate term, I will add the compensation and snubber so I can continue using this without much worry. My general use case is as a static load that starts at (near) 0 and I slowly ramp it up.

One big question I have to fill a gap in my understanding, is all of JDB's analysis uses inverting amp configuration, with negative control voltage. I don't want to be arsed to provide a dual supply right now, so I want to stick with the non-inverting configuration. My question is, in all of my analysis I have a Negative Phase Margin, which makes sense for a non-inverting amp. But everything you read says phase margin must be positive for stability. I saw this exact question posed in the JDB thread but not sure I saw an answer.

edit: I just needed to read the thread more LOL. JDB goes on to address this on page 3...
« Last Edit: January 27, 2025, 05:35:27 am by henmill »
 

Offline Konkedout

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Re: Just another DC Load
« Reply #11 on: January 27, 2025, 05:29:02 am »
Here is a photo of mine, built about 20 years ago and still working well.  I hand wired it at the time.

The linear fets are a good idea but I used "FETlingtons":  Each current range uses a darlington made with one MTP3055E MOSFET and two or four TIP41C bipolar transistors.  That works OK unless you need the load voltage to go down below 2V or so.

I would post a schematic but I don't think I have one.  I used a 10 turn panel mounted potentiometer.  It will go to 60V or 20A but not both at the same time.  The fan is controlled by a thermistor and that has NEVER turned on.

Each range uses one op amp to control the MOSFET.  Be sure to provide compensation AC feedback around the op amp by itself so as to insure stability.
« Last Edit: January 27, 2025, 05:32:23 am by Konkedout »
 

Offline henmillTopic starter

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Re: Just another DC Load
« Reply #12 on: January 27, 2025, 06:02:10 am »
I love it! You get what I'm going for haha. Except yours seems very well thought out and you welded a custom frame? *salute*

Here is a pic of what I did to update the compensation network, but as a fool I used a 10nF cap. Will likely change to a 200pF one I have as all the sims point to this direction (<1nF)

Also attached pic of another heatsink I have that I am considering because I could more easily mount the FET to a perpendicular PCB. (reduce parasitics yes?)

This is why I come here, such a wealth of knowledge so generously shared. Thank you all for your input :)
 

Offline Jay_Diddy_B

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Re: Just another DC Load
« Reply #13 on: January 27, 2025, 10:12:08 pm »
Hi,

I just to let you know that I have seen this thread.
I want to thank the people that pointed user henmill to the thread that I started on the dynamic load.

If you have any question for me, please ask.

Regards,

Jay_Diddy_B
 
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Online temperance

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Re: Just another DC Load
« Reply #14 on: January 27, 2025, 10:55:15 pm »
Quote
I want to thank the people that pointed user henmill to the thread that I started on the dynamic load.

I know three working dummy loads on this forum and your version has been properly documented. All the others are from people who don't understand the feedback / MOSFET drive requirements.

Quote
I went through an early proto stage with some random IRF FETs I had access to just to prove out the control board. Then I weighed my options between buying a few cheapish power FETs, without SOA for DC, maybe designing a PCB, or just doing it right by starting with an IXYS Linear FET. So I paid a little under 9 American Dollarbucks for a IXTH80N075L2, just so I could go full overkill and feel safe about not blowing this thing up (easily).

I'm not sure if this MOSFET can be driven directly by the LMC6484. The data sheet doesn't state the open loop output resistance so it is unknown at which point the drive circuit will run out of steam. (The op amp can't supply more current) From the data sheet of the IXTH80N075L2 you can see that CISS is 4 nF. The IRF520 is only 350 pF.

If the op amp can't drive the FET it is easy to add some buffer amplifier with some resistors, diodes, and two transistors.

Edit: Something like this:



The driver is very fast and for the LMC6484 R-Comp and C-Comp will not be required. Faster op amps might require some compensation.


« Last Edit: January 27, 2025, 11:19:18 pm by temperance »
 

Offline Jay_Diddy_B

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Re: Just another DC Load
« Reply #15 on: January 28, 2025, 03:01:20 am »
Hi,

Here is a little analysis on the buffer circuit proposed by temperance:



When given a 0-15V the ramp, the output of the buffer circuit changes from 3V to 9.2V.




The AC gain is -7.8dB:




Where does the AC gain come from?

Gain = 20 log  (R3 // R2) / R5 + (R3 // R2) =  20 log (0.68k / 1.68k) = -7.85 dB

R3 // R2 means R3 in parallel with R2

Regards,

Jay_Diddy_B

 

Offline henmillTopic starter

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Re: Just another DC Load
« Reply #16 on: January 28, 2025, 03:50:44 am »
@Jay_Diddy_B - thanks for chiming in, pleased to have you here! I will absolutely have some questions for you.

@temperance - if anything, I will drop in a more appropriate opamp and save this one for another project. I'm sure there are some out there, but given a max output current of 30mA, is the concern that the amp would not be able to supply enough current to slew the gate fast enough to regulate? This should all depend on the nature of whatever transient it is reacting to, right? What is a back-of-the envelope number to start with, in terms of step transient edge rate, so I can design around that? How much more output current (or other spec: GBW, slew rate?) do I need?

Sorry that's a lot of question marks I threw at you. Am I thinking about this the right way? Given I am also a novice at amplifier building, I'd rather not add the parts and complexity to this design. But I appreciate the tip.

@Jay_Diddy_B - One question to start, is how do you determine most of those model parameters as you show (and provided, thank you) from the MOSFET datasheet? I can't imagine you can know all those geometries of the device. Is it just important to get things like Vth, gfs, all the capacitances? I found this ltwiki info on the parameters which is helping, but yes if you have any guidance here I'd really appreciate it. https://ltwiki.org/LTspiceHelp/LTspiceHelp/M_MOSFET.htm

pre-edit: Ok, I just realized there is a model available for the part in your example... I thought you had cobbled together a model, is that the case?

If not, how do you recommend I make an accurate sim of my device? Can I edit individual parameters of a similar part to get me close?

Thanks to you all in advance!
 

Offline henmillTopic starter

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Re: Just another DC Load
« Reply #17 on: January 28, 2025, 04:29:29 am »
I went back to your thread because I suddenly remembered you did a buildup of a simplified mosfet model, so following that and pulling from my datasheet, attached is what I have. I also inserted my opamp. Next I will change the circuit to match what I have IRL, but eagerly await your advice on how best to model my chosen FET, without mfg provided spice model.

Thanks!

IXTH80N075L2 datasheet:
https://www.littelfuse.com/assetdocs/littelfuse-discrete-mosfets-ixt-80n075-datasheet?assetguid=09b664e9-c301-4232-b44a-1bb876c4d880

 

Online temperance

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Re: Just another DC Load
« Reply #18 on: January 28, 2025, 11:27:17 am »
Quote
When given a 0-15V the ramp, the output of the buffer circuit changes from 3V to 9.2V.

I just put this together quickly and didn't take care of the offset. You can remove R3 if the off-set is too large. This changes the gain but that is not important. The gain is anyhow less than 1.

Quote
@temperance - if anything, I will drop in a more appropriate opamp and save this one for another project. I'm sure there are some out there, but given a max output current of 30mA, is the concern that the amp would not be able to supply enough current to slew the gate fast enough to regulate? This should all depend on the nature of whatever transient it is reacting to, right? What is a back-of-the envelope number to start with, in terms of step transient edge rate, so I can design around that? How much more output current (or other spec: GBW, slew rate?) do I need?

For a correct analysis of the circuit you need to know the open loop output resistance of the op amp. The op amp you want to use doesn't state this resistance directly but the text mentions to calculate this from the saturation and load numbers given in the data sheet. The circuit you obtain is an RC low pass filter and the output of this network (in this case the voltage across the current sense resistor) is fed back into the op amp. The required analysis is here:

https://www.eevblog.com/forum/projects/dynamic-electronic-load-project/msg462562/#msg462562

This should give you an idea about the required gate resistor for IXTH80N075L2. If you don't have the model, you can use Ciss which is Cgd + Cgs instead.

R2 in the analysis is the external gate resistor summed with the open loop output resistance of the op amp. (you need to add some external resistance because the output stage of most op amps can't drive the capacitance directly without oscillating. Safe values are probably larger than 47 R.)
 

Offline sorin

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Re: Just another DC Load
« Reply #19 on: January 28, 2025, 03:19:25 pm »
Have a look of this AN from Microchip.
Some OpAmps need a few kilo Ohm of resistance to be stable when driving capacitive loads.
« Last Edit: January 28, 2025, 03:24:17 pm by sorin »
 
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Offline henmillTopic starter

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Re: Just another DC Load
« Reply #20 on: January 28, 2025, 04:32:06 pm »
Hi guys. Respectfully, I am aware of the need for isolation resistance when driving a capacitive load with an opamp. Originally, I used a 470R to "play it safe" and was nudged to reduce it to something more like 10-100R. I chose 47R arbitrarily but have not yet tested, I want to get the simulation right first. Most likely I will increase it to 100R.

About output resistance, this seems to be rarely specified. But can I estimate it from this figure from the datasheet?


My conditions are Vs = 12V, and the output voltage will typically be in the range of about 4-9V. The chart starts to level off around 5-6V to somewhere between 20-30mA. From Ohm's law, this puts us in the range of 200-300 ohms (4V/20mA - 9V/30mA). I realize this is not the same as Zout, but could this serve as a good enough approximation?

Would anyone like to comment on my simplified mosfet model shown a couple posts up? Using transconductance, Ciss, Crss, and Vth from the datasheet, and the approximated Rout of the opamp, is this enough to start tuning for stability? Actually, about the Rout, shouldn't that be captured in the spice model? Do I really need to include it as extra resistance?

Ok, I'm editing before posting again, but leaving my original comments about output impedance. The TI reference design includes a plot of Zo vs frequency:


 

Offline Kleinstein

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Re: Just another DC Load
« Reply #21 on: January 28, 2025, 04:52:41 pm »
The curve shown can not be used to get the dynamic output impedance. This is only for the required headroom. Z_out is generally higher.

The 2015 version of the LMC648x datasheet has the output impedance as figure 62. It gives some 300-400 ohm for the relevant frequencies.
The simple OP-amp models don't include the R_out part of the model. Adding the resistance gives a better model and could really make the difference.
One may still want the physical gate resistor so that the OP-amp does not oscillation - R_out of the OP-amp does not help here, it is more the reason for limited capacitive drive capability.
 

Online temperance

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Re: Just another DC Load
« Reply #22 on: January 28, 2025, 06:31:23 pm »
Quote
The 2015 version of the LMC648x datasheet has the output impedance as figure 62. It gives some 300-400 ohm for the relevant frequencies.

Interesting. The new data sheet doesn't quote any number but states to calculate the open loop output resistance from the saturation numbers...

This is rather high if you want to drive an IXTA80N075L2 with an equivalent input capacitance of 4 nF at some reasonable speed. But of course it depends on the response time you have in mind.

Quote
Would anyone like to comment on my simplified mosfet model shown a couple posts up? Using transconductance, Ciss, Crss, and Vth from the datasheet, and the approximated Rout of the opamp, is this enough to start tuning for stability? Actually, about the Rout, shouldn't that be captured in the spice model? Do I really need to include it as extra resistance?

That seems about right with the transconductance being 12 and the values chosen for Crss, Ciss.

Edit:
Quote
Actually, about the Rout, shouldn't that be captured in the spice model? Do I really need to include it as extra resistance?

It seems the model contains Zo open loop. From the spice file: *OPEN-LOOP OUTPUT IMPEDANCE VS. FREQUENCY (Zo). What follows are some calculations and references. Maybe someone versed in reading those can make sense from that?

Source for the spice model:
https://e2e.ti.com/support/amplifiers-group/amplifiers/f/amplifiers-forum/703385/lmc6484-lmc6484-spice-model
« Last Edit: January 28, 2025, 06:49:43 pm by temperance »
 

Online temperance

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Re: Just another DC Load
« Reply #23 on: January 28, 2025, 08:10:37 pm »
Miller capacitance simulation.

If the drain voltage is constant, the capacitance seen by the driver is Ciss. In reality there is some impedance / resistance in series with the drain and the miller capacitance starts to dominate. Placing sensible source resistance / impedance values in the simulation for those is somewhat difficult and a trade off.

To be safe I would increase the source inductance towards 2 µH.
 

Offline henmillTopic starter

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Re: Just another DC Load
« Reply #24 on: January 28, 2025, 10:36:31 pm »
This is rather high if you want to drive an IXTA80N075L2 with an equivalent input capacitance of 4 nF at some reasonable speed. But of course it depends on the response time you have in mind.

So this requirement I am not sure about. For now, I don't mind having a slow response if I have guaranteed stability with the parts I have on hand. But, I have been so enlightened by this thread and others linked, that I will likely expand this design to include the pulsed current added on top of the constant current, as Jay_Diddy_B has so thoroughly documented. But first I will refine the physical design to reduce all the parasitics, and generally improve the system.

Miller capacitance simulation.

If the drain voltage is constant, the capacitance seen by the driver is Ciss. In reality there is some impedance / resistance in series with the drain and the miller capacitance starts to dominate. Placing sensible source resistance / impedance values in the simulation for those is somewhat difficult and a trade off.

To be safe I would increase the source inductance towards 2 µH.

Let me make sure I understand, you suggest I should add an inductance between the source terminal and the sense node for simulation? I do have a longish wire from the FET down to the control PCB, so that makes sense to me. And even longer wire for the return out to the front panel terminal. But everything in the control board is referenced there, so maybe it doesn't make sense to include an inductor from low side of sense R to GND.

The curve shown can not be used to get the dynamic output impedance. This is only for the required headroom. Z_out is generally higher.

The 2015 version of the LMC648x datasheet has the output impedance as figure 62. It gives some 300-400 ohm for the relevant frequencies.
The simple OP-amp models don't include the R_out part of the model. Adding the resistance gives a better model and could really make the difference.
One may still want the physical gate resistor so that the OP-amp does not oscillation - R_out of the OP-amp does not help here, it is more the reason for limited capacitive drive capability.


Understood, thank you for finding that info. I am not trying to eliminate the gate resistor, just trying to piece together a good simulation in order to find the optimal value.

The next tasks I will try to clear are:
 1) Generate Zout curve as done in reference design, but with non-inverting amp and 12V supply
 2) Follow Jay_Diddy_B's analysis for my system with Rout and my simplified model
 3) In parallel, shop for another opamp that can be had for around $2, especially if I struggle to meet stability criteria with LMC6484

I will no doubt be following up asking lots of sophomoric questions about the simulations.

Thank you all again for the help!
 


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