Just another DC Load

[temperance]

Let me make sure I understand, you suggest I should add an inductance between the source terminal and the sense node for simulation? I do have a longish wire from the FET down to the control PCB, so that makes sense to me. And even longer wire for the return out to the front panel terminal. But everything in the control board is referenced there, so maybe it doesn't make sense to include an inductor from low side of sense R to GND.

That's a misunderstanding. "source" In this context is the power source under test or V3. As such I was referring to L1 in this post by Jay_Diddy_B:
https://www.eevblog.com/forum/projects/dynamic-electronic-load-project/msg288555/#msg288555

The inductance present in the simulation is the wiring between the voltage source V3 and the drain of the MOSFET. Without the inductance, the capacitance seen by the op amp is Ciss because the drain voltage is constant. By adding L3 the miller effect comes into the picture. The voltage gain (Vds/Vgs) increases with increasing frequency as the impedance of L3 increases. The snubber takes care of keeping the gain low.

The inductance of L3 is, as I wrote a trade off. A total wiring length of 1 meter between the source under test and MOSFET drain is slightly less than 1 µH. For my taste 1 µH is not enough but this might be fine for what you envision. I would aim for 1.5...2 µH.

Breadboard wiring:
A proper solution can be a star GND construction.

-Choose a reference point. That's the GND side of the sense resistor in this case.
-Minimize the wiring length as much as possible between the source of the MOSFET and the sense resistor. (And for a high speed load you will need a low inductance resistor or a normal resistor with a snubber across the resistor or some other method to compensate the resistor inductance like an RC low pass filter.)
-All op amp related GND's go to the star GND point each with their own wire. (Reference GND, op amp GND,...)
-The GND of the source under test must also connect to this star point.
-The same goes for the snubber. The other end of the snubber must be close to the MOSFET drain.

The reference point for all measurements is also the star connection.

When not done properly, the output signal (the current in the power loop) might for example couple into the op amp inputs trough a common resistance and cause all sorts of problems because the layout problems are now amplified by the op amp.

Some people are much better at explaining this. More information can be found here:
https://www.analog.com/en/resources/analog-dialogue/studentzone/studentzone-march-2017.html

More links on the bottom of that page.

Edit: Jay_Diddy_B shared pictures of a PCB with a GND plane. You can also take a look at those.

[Jay_Diddy_B]

Hi,

In this model:



The value for the transconductance is too low.

The transconductance can be estimated from this graph on the MOSFET datasheet:




Gm = delta Id / Delta Vgs = 50A - 20A / (7V - 6V) = 30

Using a value of 30 will be pretty safe.

Jay_Diddy_B

[Jay_Diddy_B]

Hi,

If I put the MOSFET parameters into an AC model, to measure the control loop gain. I get the following result:




The simulation is showing that I have a stable control with the values shown.

Regards,

Jay_Diddy_B

 ac analysis.PNG (116.74 kB. 1912x916 - viewed 28 times.)

[Jay_Diddy_B]

Hi,

Looking at the same circuit in the time domain:





This is a very nice transient response.

Regards,

Jay_Diddy_B

[Jay_Diddy_B]

Hi,

There is a common belief that you need a lot of Gate drive in a dynamic load. This belief is wrong:



The simulation shows that less than 300uA is needed.


Jay_Diddy_B

[Jay_Diddy_B]

Hi,
and the positive edge, a similar result:





Jay_Diddy_B

[Jay_Diddy_B]

Hi,

When it comes to building the circuit, the sense resistor in the Source of the MOSFET, should be a 4-wire resistor.

The bottom Kelvin connection should be the small-signal ground for the circuit. It should be connected to the star point.





Regards,

Jay_Diddy_B

[henmill]

That's a misunderstanding. "source" In this context is the power source under test or V3. As such I was referring to L1 in this post by Jay_Diddy_B:
https://www.eevblog.com/forum/projects/dynamic-electronic-load-project/msg288555/#msg288555

The inductance present in the simulation is the wiring between the voltage source V3 and the drain of the MOSFET. Without the inductance, the capacitance seen by the op amp is Ciss because the drain voltage is constant. By adding L3 the miller effect comes into the picture. The voltage gain (Vds/Vgs) increases with increasing frequency as the impedance of L3 increases. The snubber takes care of keeping the gain low.

The inductance of L3 is, as I wrote a trade off. A total wiring length of 1 meter between the source under test and MOSFET drain is slightly less than 1 µH. For my taste 1 µH is not enough but this might be fine for what you envision. I would aim for 1.5...2 µH.

Ok, got it, yup I understand that as I've followed along Jay_Diddy_B's posts. Thank you for the detailed explanation. I am thinking of ways to reduce the inductance of the wiring inside the box. I think this will be important because I want to take advantage of the existing fans and put the heatsink(s) right in front of them. But a really compact form factor as Jay_Diddy_B presented would obviously make a lot more sense for this aspect. I'm sure the 8-10" or so of sloppy wiring and poor coupling between the pos/neg wires is adding an appreciable inductance.

See attached annotated images of the board as it is now. It could be better, but for protoboard implementation I think it's ok. I tried to beef up the traces where I had to bring in current and kept length of that path to a minimum. I also attempted kelvin connections to the two opamps sensing nodes. If I stay in this rabbit hole side project long enough, I'll probably make a proper PCB and really try to maximize the potential of the FET.

The value for the transconductance is too low.

Gm = delta Id / Delta Vgs = 50A - 20A / (7V - 6V) = 30

Using a value of 30 will be pretty safe.

Jay_Diddy_B

Oh! Thanks for the correction. I took the value 12 from this chart of g_fs, which admittedly I don't know the difference. I remember g_m from my studies, but I just saw a graph titled "Transconductance" and went for it.


THANK YOU for this quick and pointed check of my FET in simulation. Next I will ask about the non-inverting version of this for single ended supply, but I need to gather those thoughts first.

[Jay_Diddy_B]

Hi,

This shows how the value of Gm changes the control loop response:




I didn't see the Gfs curve on the datasheet, most datasheets don't have one.

Jay_Diddy_B

[temperance]

Wow, Jay_Diddy_B

extremely nice of nice of you.

About Gm. Gm at lower drain currents is in the range of 10...15. But indeed, thinking about it choosing Gm higher is safer.

There is a common belief that you need a lot of Gate drive in a dynamic load. This belief is wrong:

I would not say "wrong". It depends on the required response. The buffer I've shown places the pole created by the MOSFET driver / MOSFET Ciss much higher up in frequency and can settle in less than a few µs or even faster. An other disadvantage of a "weak" driver is poor transient rejection because the driver can't clamp the gate voltage while the control loop is lagging and while current is injected into the gate trough Cgd with some applied voltage step. The buffer I've shown has almost no overshoot because the biased PNP transistor is clamping the MOSFET gate.

The case for the voltage step is where you pre-bias the load trough a low voltage auxiliary power supply and a diode to avoid the control loop from going into saturation. But I admit this is a special case and not everyone needs such a fast control loop.

[sorin]

There is a common belief that you need a lot of Gate drive in a dynamic load.
The simulation shows that less than 300uA is needed.

First, I want to thank you for sharing your knowledge with the community here!

But, I'm not so sure about this.
For example, what happens when you connect the load to the power source?
What happens when you go from 0A to full load?
What happens when the tested power supply changes from 5V to 15V?

[henmill]

@sorin and @temperance, you are both saying the same thing, it depends on the performance requirements you need. If we are to expect to test huge load steps, seeing 10's of V/us, sure I could need a stronger gate drive. Or if I want to continuously pulse a step current like Jay_Diddy_B's dynamic load, and especially if the frequency is into the kHz. Yes I would need stronger gate drive.

For now, I will be happy to know that this version will not oscillate if I accidentally give it a strong transient. For now this will be used like a constant current load that I always ramp up slowly from zero.

If/when I get around to adding the pulsed feature, I will probably choose a different opamp and even consider a dedicated buffer stage. I'm also feeling very tempted to add some digital features like Power calculation, temperature readouts, digital current set, etc etc. We'll see.

Anywho, I've updated the AC Analysis ltspice circuit (attached), and included the power resistor, as well as return lead inductance. Also made it reflect my implementation with non-inverting amp, single supply, my opamp model etc. With the same values as Jay_Diddy_B, I am seeing what I think is very stable response. Phase margin of ~55 deg.







Let me know how else I can tune this circuit! Now I'm updating the full "mini load" sim with these parts to see the load stepping behavior.

Cheers!

[sorin]

I don't know very much about control loop design, but i think that you can not simulate a MOSFET with a current source. Especially in the case of transit response when the power varies from 0V - (to something) or when the current varies from 0A - (to something).
Tray to substitute the current source with IRFP250N, and you will see a different transit response.

Code: [Select]

.model IRFP250N VDMOS(Rg=1.44 Vto=4.0 Rd=47m Rs=0m
+Rb=5.6m Kp=13 Cgdmax=3.9n Cgdmin=0.10n Cgs=1.9n
+Cjo=1.25n Is=5p tt=186n mfg=International_Rectifier Vds=200 Ron=75m Qg=123n)

For now, I will be happy to know that this version will not oscillate if I accidentally give it a strong transient. For now this will be used like a constant current load that I always ramp up slowly from zero.

If this is the case, I would suggest you use a cheap OpAmp like LM358. Remember to avoid cross-over distortion. Or a better one is the MC34072 (only $0.3 @LCSC) which has a Capacitance Drive Capability of 10nF.  You can also use a cheap MOSFET transistor like K3878 (only $1 @LCSC). The LT1014 cost around $4.5

[henmill]

I don't know very much about control loop design, but i think that you can not simulate a MOSFET with a current source. Especially in the case of transit response when the power varies from 0V - (to something) or when the current varies from 0A - (to something).
Tray to substitute the current source with IRFP250N, and you will see a different transit response.

Others can correct me, but the small signal model of a mosfet is a voltage controlled current source. Granted, this version would not capture many of the effects transitioning into/out of different operating regions, but should capture the core function of the device.

I did it this way following along Jay_Diddy_B's guidance for another user in his Dynamic Load thread.

No kidding I'll get a different response if I use a different part. The point is to try to model my chosen part, which I am already using, as best as I can. From my limited understanding, the factor that plays the biggest part in stability is the capacitance seen at the gate. Which is complex and changes dynamically, but what I have now is a decent approximation. If IXYS provided a SPICE model, I would use it. But they do not for my chosen model.

I don't seen any advantage in switching to LM358 (really I would want 324 the quad version, but guess what they don't make it in DIP). It has similar output current limit and 100pF capacitive load drive. At a glance, the MC3407(4) looks promising, but a quick survey of suppliers says the quad version in DIP is not in stock anywhere.

The goal here is to gain confidence that I can use the parts I have already with the right compensation. So far, it's looking like it is not impossible. Though if I could go back in time, I might have chosen a different opamp for this purpose. I am using a spare that I have on hand for a different project.

One of the primary goals of this project is to spend as little money as possible on it! I am not going to buy a new opamp unless I absolutely have to. And I'm definitely not going to sub out my linear FET.

It seems these aspects of the project keep getting forgotten by some on here..

[Kleinstein]

The DIP version of the LM324 would be no issue. For the MC34074 it looks like there was never a DIP version.
The main point is getting an OP-amp that is single supply and thus can work down to the negative supply.
Another option, a bit similar to the MC34074 is the TLC274.
I don't see a need for quad OP-amp - only 2 of the amplifiers are critical. As dual there is the LT1013 as a version with good accuracy, if this is wanted.

[temperance]

If an LM358 fits your application depends. The offset current= op amp offset voltage / Rsense or 20 mA for 2 mV offset with a 0R1 sense resistor.

The model is fine. Unlike your MOSFET model, transconductance is non linear in a real MOSFET. But you've set Gm to be 30. Anything lower than 30 will only improve phase margin because the MOSFET voltage gain decreases. It is anyhow a trade off because the voltage gain depends on the wiring inductance and the snubber.

Crss dependen on Vds. You could try higher values for Crss as the value of 325 pF applies for Vds= 20 V. Crss is 700 pF with Vds is 5 V and 1 nF at 2.5 V Vds. (Crss is taken from Fig.11 from the data sheet) I think this is more realistic.

You've modeled two inductors in series with the supply under test. This is not required as the supply under test can be replaced by a short for AC signals (up to some frequency in real life).

[Jay_Diddy_B]

Hi,

The LT1014 is really a trimmed version of an LM324.


From the ADI (Linear Technology) datasheet:

The LT®1014 is the first precision quad operational amplifier
which directly upgrades designs in the industry standard
14-pin DIP LM324/LM348/OP-11/4156 pin configuration.
It is no longer necessary to compromise specifications,
while saving board space and cost, as compared to single
operational amplifiers



The main feature is reduced input-offset voltage.

The other features that are common to between the LM324 and LT1014

The common mode input includes ground and the output can swing close to ground. By ground it means the negative supply voltage in single-supply applications.

The datasheet says:

 Both the LT1013 and LT1014 can be operated off a single
5V power supply: input common mode range includes
ground; the output can also swing to within a few millivolts
of ground. Crossover distortion, so apparent on previous
single-supply designs, is eliminated. A full set of specifications
is provided with ±15V and single 5V supplies


The LT1013 is a better LM358

and the LT1014 is a better LM324

The LTspice library does not include the LM358 and LM324. The LT1013 is a suitable substitute.


In the Jay_Diddy_B original design I used dual power supplies, +/-9V. I did this to make summing of the static reference and the dynamic reference easier. The dual-supply allowed me to use a wide range of op-amps that don't need include the negative supply rail in their input common mode range.


Jay_Diddy_B

[Jay_Diddy_B]

Hi group,

I am going to explore buffering the output of the op-amp using LTspice models. You can decide if the extra complexity is worth the results.

I replaced the transconductance model of the MOSFET with a real MOSFET model.

Unbuffered





Ideal Buffer

The voltage-controlled voltage source E1 has a gain of 1.



Practical Buffer - 4 BJTs - Diamond Buffer

This is based on the circuit of the National Semiconductor LH002



Regards,

Jay_Diddy_B

[henmill]

The DIP version of the LM324 would be no issue. For the MC34074 it looks like there was never a DIP version.
The main point is getting an OP-amp that is single supply and thus can work down to the negative supply.
Another option, a bit similar to the MC34074 is the TLC274.
I don't see a need for quad OP-amp - only 2 of the amplifiers are critical. As dual there is the LT1013 as a version with good accuracy, if this is wanted.

Thanks, I guess I was mistaken on the M340xx. Anyhow, if I feel the need to buy a new one I will likely start with the Digikey filter and work from there. Sometimes it's easier to start by filtering out what is available and in my price range, package, etc. TLC274 looks nice.

I mostly want a quad to keep my current board going, maybe make a new one but in the same style. I need one amp for buffered reference, one for the gate, and another for panel meter. The 4th I want available in case I implement some kind of overcurrent detection/prevention. Or I could have a second FET for more power. Etc.

If an LM358 fits your application depends. The offset current= op amp offset voltage / Rsense or 20 mA for 2 mV offset with a 0R1 sense resistor.

The model is fine. Unlike your MOSFET model, transconductance is non linear in a real MOSFET. But you've set Gm to be 30. Anything lower than 30 will only improve phase margin because the MOSFET voltage gain decreases. It is anyhow a trade off because the voltage gain depends on the wiring inductance and the snubber.

Crss dependen on Vds. You could try higher values for Crss as the value of 325 pF applies for Vds= 20 V. Crss is 700 pF with Vds is 5 V and 1 nF at 2.5 V Vds. (Crss is taken from Fig.11 from the data sheet) I think this is more realistic.

You've modeled two inductors in series with the supply under test. This is not required as the supply under test can be replaced by a short for AC signals (up to some frequency in real life).

Thank you for pointing out the Crss behavior, I will definitely step through some values and see how performance changes.

About the inductor in series with the DUT return, I thought it just made sense if we were including it on the positive side. Often times a source will be hooked up with longish leads that aren't well coupled.

Or is it that there is just no interaction with the stray inductance beyond the control's reference? So it doesn't matter for the control stability? (thanks for helping my understanding in advance)

[henmill]

Hi everyone,

Sorry for the extended lack of updates. Lost some steam via lack of free time, but I also detoured to rework the thermals and layout of the system to get it to it's temporary final state so I can get back to other work.

Recently I've spent an embarrassing amount of time dinking with the sims, but realized a mistake the other day that has unlocked my ability to move forward

Earlier in this thread I said one goal of the project was to use as much of what I have on hand and spend as little as possible. But I was lacking capacitor values between 200p and 10n, and also wanted some NTCs to incorporate, so I also shopped around and ordered some LM324 and TLV2374, just in case I have problems with the LMC6484. I still don't want to sink much $ into this project, but I will take any excuse to enhance my library of parts haha.

So, starting with the new thermal/layout concept:

I switched to a short, wide, finned heatsink, mostly because the other one I could not quite fit comfortably enough to close the lid. Not sure if this new sink is optimal but I would think I could dissipate 50W continuously. I need to do more research to back that claim up though, but will likely just test it empirically





Now, onto the simulations. I've done some comparisons between the LMC6484 and TLV2374 with the simplified small signal model of my part IXTH80N075L2, as well as the model provided for a different IXYS part, used by a different user that Jay_Diddy_B also helped out. That part number is IXTN4650L, and you will notice it has even higher apparent capacitance Ciss compared to my part. So to me a reasonable hypothesis is that if my configuration is stable driving either part, there is a good chance it will be IRL.

In addition, I ran the simulation at Vin of 5V and 25V, and adjusted my model based on the datasheet values of Ciss, Crss vs. VDS:


To summarize, attached are sims showing phase margin for the following:

opamp     |     Mosfet     |     VDS     
LMC6484  | IHXTH80N.. |    5V
LMC6484  | IHXTH80N.. |    25V
LMC6484  | IHXTN46N.. |    5V
LMC6484  | IHXTN46N.. |    25V
TLV2374   | IHXTH80N.. |    5V
TLV2374   | IHXTH80N.. |    25V
TLV2374   | IHXTN46N.. |    5V
TLV2374   | IHXTN46N.. |    25V

Long story short, I think I am safe to use the LMC6484, but might swap it out anyways to save it for something where its features can shine more. Please let me know any thoughts you have regarding my methodology and reasoning!

I will get around to running transient sims eventually...

Here is the schematic used for all these, in which I swapped the opamp and mosfet around to compare.


Another detail, I have decided to ditch the idea of using a big power resistor in series. With the parts I have, even at 1 ohm resistance I will be limiting my testable current to 5A at 5V (at best!) and I would like to have the ability to sink more at the low voltages, just in case! If anything, I might rig up a disconnect with overcurrent trip, or a plain old regular fuse.

There is probably more I could say, but I want to get this out here for comment.

Thanks as always for feedback!

[henmill]

(Continued due to attachment limit)

Here is the schematic showing the other mosfet in use:

[RoGeorge]

You may want to read about "ako" (a kind of) feature in LTspice.
https://ltwiki.org/index.php?title=Undocumented_LTspice

"ako" is very useful when comparing the outcome of running the same schematic with different parts, so you won't have to compare them manually.  LTspice can ".step" the model of a component just the same as you ".step" the value of a parameter, and can show them all on the same plot.

Same for the phase margin.  You write a ".meas" to find the phase margin, define ako models for each op amp type (or for each MOSFET type), then .step the .ac simulation.  Then look at the log file (usually opens with CTRL+L) to see the values of the phase margins for all the op amp you stepped through.

[henmill]

Thank you for the tip! That does sound much more efficient than what I've done to this point. It was a bit tedious running and re-running making sure I've got the differences right.

[Jay_Diddy_B]

Hi,

Here is a much faster model. I used the SPICE model for the MOSFET from Littelfuse. I could not find the exact part, so I used another similar part:



The SPICE model is pasted on the schematic. If you do this you don't need the .lib directive and the .asc file is self contained.

This runs in the frequency domain.

After running the model plot V(a)/V(b) to get the loop gain.


I have attached the model.

I used an op-amp from the LTspice library.

Regards,

Jay_Diddy_B

 IXTH30N60L2 version.JPG (112.98 kB. 1456x730 - viewed 22 times.)

[Jay_Diddy_B]

Hi,
With the faster model you try things easily. Here is an more optimized circuit, for this MOSFET:



Regards,

Jay_Diddy_B