Just another DC Load

[henmill]

To quote Dave: "Hi!"

I've been working on a DIY DC Load for m'lab. It started as most DIY DC Loads start I imagine: because you need a frickin adjustable load to test something! In my case, a silly mod to 15V power supply.

The goal was to first and foremost use stuff I have on hand or could have for cheap/free. So I ended up up-cycling a couple heatsinks and using a small 2U server PC case I have. It has been sitting unused for at least 3 years so I figured why not. I also happened to have an old ATX power supply that was hacked up and used briefly as my bench 5V and 12V supply. [Light bulbs coming on everywhere]

Originally I wanted to put it in a spiffy extruded case like one of those automotive inverters, but couldn't find a free one fast enough. But the PC case is pretty cool I think, albeit big. With all the space, it might eventually morph into a horribly hacked semblance of an SMU one day....

The performance goal was to be able to sink at least 50W at up to 24V. The 2nd proto (probably temporary final version) is able to do that pretty easily.

I went through an early proto stage with some random IRF FETs I had access to just to prove out the control board. Then I weighed my options between buying a few cheapish power FETs, without SOA for DC, maybe designing a PCB, or just doing it right by starting with an IXYS Linear FET. So I paid a little under 9 American Dollarbucks for a IXTH80N075L2, just so I could go full overkill and feel safe about not blowing this thing up (easily).

So here's the rundown of the design, and I'd love any input on what I should add, such as protections, improvements etc.

DCin --> Power Resistor (2 or 4 ohms) --> IXYS Linear Fet --> 100mR Sense Res -- GND
Quad op amp to buffer control input from 10-turn Pot, scale it down by 10, drive powerFEt, provide scaled Vout to panel meter
Up-cycled PC heatsinks for the FET and power resistors
Amazonian banana binding posts and power resistors. Have 5x 4R 100W resistors. Considering 2S-2P configuration if I can find the right heatsink

You can see all the pictures here: https://imgur.com/a/dc-load-linear-power-mod-xqmjoMd

Having trouble attaching more than one pic due to file size? Gotta get to bed but will direct upload more pics later.

Cheers!

[drksy]

-why are you buffering Vpot twice?
-u4 needs compensation, otherwise this is just an oscillator. You need some 100p - 10n ceramic cap from u4_in_- to u4_output, remove the wire from u4_in_- to r_sense_+, and add a resistor instead (~10k - 100k) between u4_in_- and r_sense_+. With LMC648 probably 10k and 1n are sensible.
-what are those r_power resistors above the mosfet doing?
-you need some bulk decoupling for vcc, ~100u electrolytic in addition to some other ceramic caps in parallel, 1u + 100n + 10n, 10n as close to u4_vcc as possible.
-that 3d printed plastic clamp might melt and stink when you heat up the mosfet with a significant load. I would use some metal holder/screws instead.

Give this video a watch https://www.youtube.com/watch?v=vd5IBFFjnOc, shows how it's done (see pic for schematic)

overall: jank/10  But keep improving

[MarkF]

Some links to other EEVBlog DIY electronic loads:

  https://www.eevblog.com/forum/projects/dynamic-electronic-load-project/

  https://www.eevblog.com/forum/beginners/a-load-off-my-mnd/msg2151265/#msg2151265

[henmill]

Hi drksy, thanks for the feedback. I'll address your comments point-by-point:

- buffering Vpot twice: Well no good reason really, I think I did it because I was changing up the configuration and it was convenient, and I thought this was a good way to use one of the unused opamps instead of terminating it. I realize this multiplies any offset error but in this case it doesn't matter too much as it is just the reference voltage. (sorry for providing a not 100% accurate schematic of what is implemented on the protoboard)

- u4 compensation: I actually do have a cap across the output to -input. I think I used a 47pF.. You might be able to point it out if you look at the close up of the PCB in the attached image.
  And thanks for the recommendation on the connection to the sense node. I thought maybe no series resistance was necessary given the very high input impedance of the op amp. Is the Res/cap combo mostly to act as low pass filter?

- power resistors: They are there to share the overall power dissipation. Probably not necessary I guess with my awesome Linear FET. Just wanted some kind of overall current limiting in case I do something stupid (high probability)

- bulk decoupling: I have a 10uF on the board where 12V comes in, and you can't see it but there is a 100nF underneath the board as close to VCC pin as possible.

- 3d printed clamp: yes I realize this is a sh*t solution for mounting. I have some PET material I may use to make a new holder that can withstand a bit higher temp. The hope is my heatsinking will be so good that the plastic will not get very warm. I tried and failed to tap the copper heatsink.

I will keep looking for a more appropriate heatsink so I can mount the FET vertically and solder into a PCB. But for now I'm pretty pleased with the performance!

Thanks again for the comments!

EDIT: I need to correct my statement about u4 compensation. I had a feedback cap for the amp driving the scaled current monitor amp, NOT the amp driving the mosfet. I am still working out the value for feedback cap as of 1/27, but am learning a lot and having fun

[Kleinstein]

The series resistor in the feedback is needed to make the capacitor work. It is the RC combination that matter. The shunt resistor is pretty low to start with. So the extra resistor is really needed to get good stability.

Another small point would be to have some RC combination across the FET from drain to source (e.g. some 100 nF and 100 ohms - I don't remember to best values). This would help against oscillation / ringing with a difficult load with a lot of low loss inductance.

The extra resistors are OK as a last line of defense (e.g. also with reversed polarity be acident). This is actually a good idea to have it.
Another way in this direction could be a fuse.

[henmill]

Kleinstein: "when you say the resistor in the feedback is needed to make the capacitor work", you are just referring to the cap from output to -input right? We are not suggesting a cap to Gnd at the -input right? I think I know the answer because adding capacitance to the inverting terminal is generally a very bad idea right?

About the idea to have RC across the FET drain to source, are you suggesting like an RC snubber? Cap in series with resistor? I could implement that, sure. Would an example where this is useful be like if I'm loading a switching regulator?

About fusing/protection, probably a good idea to have one, I'll add that to the list. But I am also thinking I could free up one of the opamps and use it like a comparator for overcurrent protection. I have some pretty beefy solid state relays (also from IXYS coincidentally) that I'm thinking to use for a means to disconnect the load.

Here's a crude schematic of what I think are the suggestions:

[Kleinstein]

The drawing is Ok. The resistor in front of the gater is normally choosen smaller, more like 50 or 100 ohms so that the OP-amps is OK with driving this resistance together with the gate capacitance.
For suitable values for the snubbers I would run the circuit through a simulation, e.g. with LTspice. Chances are the values are not that critical, though it can make a difference when testing a lab supply with the load. Some lab supply circuits can have an ouput impedance that look similar to an near ideal inductor and wihout the snubber the electronic load may oscillate with such a load, even with the compensation around the OP-amp.

If paranoid about the load, there is one more case: when the load is activated before the DUT / supply is connected the OP-amp will turn on the FET all the way and take some time to start regulating. This means there could be a large initial current pulse, that could be an issue. At least one could limit the maximum gate voltage. Ideally one would check the drain voltage and limit the control when the drain voltage is too low. This could be something in the direction of a minimal resistance for the simulated mode that is somewhat larger than the shunt plus FET R_on.

[temperance]

The only correct load is this one:
https://www.eevblog.com/forum/projects/dynamic-electronic-load-project/

The stability analysis can be found in the thread. You will need R9 and C4 for stability otherwise the MOSFET and the wiring going to the drain will form an oscillator on itself. With on itself I mean that the servo amp is not involved and compensating the servo amp doesn't help anything.

All the others including the one presented in the YT video are brilliant oscillators. Specially those with 10 K gate resistors or those using op amps with large open loop output resistance. They don't. I made simplified analysis in an other thread long ago. But it is unpleasant reading because the Dummy load crowd came to piss on me stating I'm wrong. A proof of what I stated is being presented with real hardware quickly put together to prove my point. Oscilloscope screenshots are included.

Edit: repaired my grammar.

[drksy]

The only correct load is this one:
https://www.eevblog.com/forum/projects/dynamic-electronic-load-project/

that's a pretty good design with a thorough AC analysis. I would follow that to the T, using precisely the same component values and the opamp itself. LT1013 is an excellent opamp and a much better one than OP had originally chosen for this job.

It would make for a very reliable PSU tester for transient response and such. For a more general purpose electronic load, I would be looking for features like constant-power, constant-resistance, four-wire sensing, input protections like reverse current and reverse polarity, and some software that makes it useful for battery discharge/cutoff, component characterization, etc. But then you have to draw the DIY line somewhere! With that 300Hz oscillator baked in, it seems this was purpose-built to be a fast step load.

From a learning/fun perspective, this can be a rewarding project, but really, hard to beat the 30 dollar electronic loads you find on Aliexpress that are much more useful as a general-purpose tool.

[temperance]

From a learning/fun perspective, this can be a rewarding project, but really, hard to beat the 30 dollar electronic loads you find on Aliexpress that are much more useful as a general-purpose tool.

Those $30 dummy loads are all faulty and just like many schematics found on the web very good oscillators. (Like 1...10 K gate resistors and a poor attempt at compensating the op amp which is nearly impossible with the high gate drive resistance unless you prefer a sloppy response in the ms range.)

Save yourself the trouble and buy the components shown in the Thread by Jay_Diddy_B. They don't cost that much. (Including the IRF520. Don't swap this with anything else unless you understand the requirements)

[henmill]

The drawing is Ok. The resistor in front of the gater is normally choosen smaller, more like 50 or 100 ohms so that the OP-amps is OK with driving this resistance together with the gate capacitance.
For suitable values for the snubbers I would run the circuit through a simulation, e.g. with LTspice. Chances are the values are not that critical, though it can make a difference when testing a lab supply with the load. Some lab supply circuits can have an ouput impedance that look similar to an near ideal inductor and wihout the snubber the electronic load may oscillate with such a load, even with the compensation around the OP-amp.

If paranoid about the load, there is one more case: when the load is activated before the DUT / supply is connected the OP-amp will turn on the FET all the way and take some time to start regulating. This means there could be a large initial current pulse, that could be an issue. At least one could limit the maximum gate voltage. Ideally one would check the drain voltage and limit the control when the drain voltage is too low. This could be something in the direction of a minimal resistance for the simulated mode that is somewhat larger than the shunt plus FET R_on.

To your first point about gate R, understood, I have been playing with some simulations and 100R seems like a good value in most cases. However, this is with a FET that is different than what I am using. So I need to follow some of what is described in Jay_Diddy_B's (JDB) thread because he goes through setting up a model for a specific part (i.e., to get the gate capacitances right).

About the snubber, I have a bunch of 1R 3W resistors, and options for 1uF and 2.2uF ceramic caps, so will make a snubber, probably either 1R or 2R with the cap.

To your point about brief inrush/overshoot you might call it, I have wondered about that. With gate voltage maxed on a 12V system, the FET could allow a pretty large current momentarily. I think the series Limit resistors help with that, both in terms of limiting the current and sharing power dissipation. I'm trying to think of ways to clamp the gate voltage precisely to a value that is above my expected needed value, and is done easily with the parts I have haha.

@temperance: Thank you for linking that thread, it is so valuable. I have downloaded the spice files and have been playing around both in LTSpice and TI's TINA software. The TINA software is nice because you can really quickly and easily generate plots of Gain and Phase, and calculate phase margin. But I'm not sure it is doing the same thing as the LTSpice version... and I don't have a clear example of how to setup a model for my FET like JDB shows in the post you linked. So I think I'll try to mimic the analysis in LTSpice, but TINA has been quite useful for iterating with different component values as the sim runs quite fast.

Not sure if you caught the details in my first description, but I have a chosen FET that I splurged on and do not plan to deviate from (unless I blow it up). I also want to continue to use my opamp, LMC6484, as it is plenty capable, even though I originally bought it for other reasons (ultra low leakage measurement type stuff).

So now the task is to get the simulation as true-to-life as I can, and update component values around that. I think I'll start on a better PCB/mounting solution but for the immediate term, I will add the compensation and snubber so I can continue using this without much worry. My general use case is as a static load that starts at (near) 0 and I slowly ramp it up.

One big question I have to fill a gap in my understanding, is all of JDB's analysis uses inverting amp configuration, with negative control voltage. I don't want to be arsed to provide a dual supply right now, so I want to stick with the non-inverting configuration. My question is, in all of my analysis I have a Negative Phase Margin, which makes sense for a non-inverting amp. But everything you read says phase margin must be positive for stability. I saw this exact question posed in the JDB thread but not sure I saw an answer.

edit: I just needed to read the thread more LOL. JDB goes on to address this on page 3...

[Konkedout]

Here is a photo of mine, built about 20 years ago and still working well.  I hand wired it at the time.

The linear fets are a good idea but I used "FETlingtons":  Each current range uses a darlington made with one MTP3055E MOSFET and two or four TIP41C bipolar transistors.  That works OK unless you need the load voltage to go down below 2V or so.

I would post a schematic but I don't think I have one.  I used a 10 turn panel mounted potentiometer.  It will go to 60V or 20A but not both at the same time.  The fan is controlled by a thermistor and that has NEVER turned on.

Each range uses one op amp to control the MOSFET.  Be sure to provide compensation AC feedback around the op amp by itself so as to insure stability.

[henmill]

I love it! You get what I'm going for haha. Except yours seems very well thought out and you welded a custom frame? *salute*

Here is a pic of what I did to update the compensation network, but as a fool I used a 10nF cap. Will likely change to a 200pF one I have as all the sims point to this direction (<1nF)

Also attached pic of another heatsink I have that I am considering because I could more easily mount the FET to a perpendicular PCB. (reduce parasitics yes?)

This is why I come here, such a wealth of knowledge so generously shared. Thank you all for your input

[Jay_Diddy_B]

Hi,

I just to let you know that I have seen this thread.
I want to thank the people that pointed user henmill to the thread that I started on the dynamic load.

If you have any question for me, please ask.

Regards,

Jay_Diddy_B

[temperance]

I want to thank the people that pointed user henmill to the thread that I started on the dynamic load.

I know three working dummy loads on this forum and your version has been properly documented. All the others are from people who don't understand the feedback / MOSFET drive requirements.

I went through an early proto stage with some random IRF FETs I had access to just to prove out the control board. Then I weighed my options between buying a few cheapish power FETs, without SOA for DC, maybe designing a PCB, or just doing it right by starting with an IXYS Linear FET. So I paid a little under 9 American Dollarbucks for a IXTH80N075L2, just so I could go full overkill and feel safe about not blowing this thing up (easily).

I'm not sure if this MOSFET can be driven directly by the LMC6484. The data sheet doesn't state the open loop output resistance so it is unknown at which point the drive circuit will run out of steam. (The op amp can't supply more current) From the data sheet of the IXTH80N075L2 you can see that CISS is 4 nF. The IRF520 is only 350 pF.

If the op amp can't drive the FET it is easy to add some buffer amplifier with some resistors, diodes, and two transistors.

Edit: Something like this:



The driver is very fast and for the LMC6484 R-Comp and C-Comp will not be required. Faster op amps might require some compensation.

[Jay_Diddy_B]

Hi,

Here is a little analysis on the buffer circuit proposed by temperance:



When given a 0-15V the ramp, the output of the buffer circuit changes from 3V to 9.2V.




The AC gain is -7.8dB:




Where does the AC gain come from?

Gain = 20 log  (R3 // R2) / R5 + (R3 // R2) =  20 log (0.68k / 1.68k) = -7.85 dB

R3 // R2 means R3 in parallel with R2

Regards,

Jay_Diddy_B

[henmill]

@Jay_Diddy_B - thanks for chiming in, pleased to have you here! I will absolutely have some questions for you.

@temperance - if anything, I will drop in a more appropriate opamp and save this one for another project. I'm sure there are some out there, but given a max output current of 30mA, is the concern that the amp would not be able to supply enough current to slew the gate fast enough to regulate? This should all depend on the nature of whatever transient it is reacting to, right? What is a back-of-the envelope number to start with, in terms of step transient edge rate, so I can design around that? How much more output current (or other spec: GBW, slew rate?) do I need?

Sorry that's a lot of question marks I threw at you. Am I thinking about this the right way? Given I am also a novice at amplifier building, I'd rather not add the parts and complexity to this design. But I appreciate the tip.

@Jay_Diddy_B - One question to start, is how do you determine most of those model parameters as you show (and provided, thank you) from the MOSFET datasheet? I can't imagine you can know all those geometries of the device. Is it just important to get things like Vth, gfs, all the capacitances? I found this ltwiki info on the parameters which is helping, but yes if you have any guidance here I'd really appreciate it. https://ltwiki.org/LTspiceHelp/LTspiceHelp/M_MOSFET.htm

pre-edit: Ok, I just realized there is a model available for the part in your example... I thought you had cobbled together a model, is that the case?

If not, how do you recommend I make an accurate sim of my device? Can I edit individual parameters of a similar part to get me close?

Thanks to you all in advance!

[henmill]

I went back to your thread because I suddenly remembered you did a buildup of a simplified mosfet model, so following that and pulling from my datasheet, attached is what I have. I also inserted my opamp. Next I will change the circuit to match what I have IRL, but eagerly await your advice on how best to model my chosen FET, without mfg provided spice model.

Thanks!

IXTH80N075L2 datasheet:
https://www.littelfuse.com/assetdocs/littelfuse-discrete-mosfets-ixt-80n075-datasheet?assetguid=09b664e9-c301-4232-b44a-1bb876c4d880

[temperance]

When given a 0-15V the ramp, the output of the buffer circuit changes from 3V to 9.2V.

I just put this together quickly and didn't take care of the offset. You can remove R3 if the off-set is too large. This changes the gain but that is not important. The gain is anyhow less than 1.

@temperance - if anything, I will drop in a more appropriate opamp and save this one for another project. I'm sure there are some out there, but given a max output current of 30mA, is the concern that the amp would not be able to supply enough current to slew the gate fast enough to regulate? This should all depend on the nature of whatever transient it is reacting to, right? What is a back-of-the envelope number to start with, in terms of step transient edge rate, so I can design around that? How much more output current (or other spec: GBW, slew rate?) do I need?

For a correct analysis of the circuit you need to know the open loop output resistance of the op amp. The op amp you want to use doesn't state this resistance directly but the text mentions to calculate this from the saturation and load numbers given in the data sheet. The circuit you obtain is an RC low pass filter and the output of this network (in this case the voltage across the current sense resistor) is fed back into the op amp. The required analysis is here:

https://www.eevblog.com/forum/projects/dynamic-electronic-load-project/msg462562/#msg462562

This should give you an idea about the required gate resistor for IXTH80N075L2. If you don't have the model, you can use Ciss which is Cgd + Cgs instead.

R2 in the analysis is the external gate resistor summed with the open loop output resistance of the op amp. (you need to add some external resistance because the output stage of most op amps can't drive the capacitance directly without oscillating. Safe values are probably larger than 47 R.)

[sorin]

Have a look of this AN from Microchip.
Some OpAmps need a few kilo Ohm of resistance to be stable when driving capacitive loads.

[henmill]

Hi guys. Respectfully, I am aware of the need for isolation resistance when driving a capacitive load with an opamp. Originally, I used a 470R to "play it safe" and was nudged to reduce it to something more like 10-100R. I chose 47R arbitrarily but have not yet tested, I want to get the simulation right first. Most likely I will increase it to 100R.

About output resistance, this seems to be rarely specified. But can I estimate it from this figure from the datasheet?


My conditions are Vs = 12V, and the output voltage will typically be in the range of about 4-9V. The chart starts to level off around 5-6V to somewhere between 20-30mA. From Ohm's law, this puts us in the range of 200-300 ohms (4V/20mA - 9V/30mA). I realize this is not the same as Zout, but could this serve as a good enough approximation?

Would anyone like to comment on my simplified mosfet model shown a couple posts up? Using transconductance, Ciss, Crss, and Vth from the datasheet, and the approximated Rout of the opamp, is this enough to start tuning for stability? Actually, about the Rout, shouldn't that be captured in the spice model? Do I really need to include it as extra resistance?

Ok, I'm editing before posting again, but leaving my original comments about output impedance. The TI reference design includes a plot of Zo vs frequency:

[Kleinstein]

The curve shown can not be used to get the dynamic output impedance. This is only for the required headroom. Z_out is generally higher.

The 2015 version of the LMC648x datasheet has the output impedance as figure 62. It gives some 300-400 ohm for the relevant frequencies.
The simple OP-amp models don't include the R_out part of the model. Adding the resistance gives a better model and could really make the difference.
One may still want the physical gate resistor so that the OP-amp does not oscillation - R_out of the OP-amp does not help here, it is more the reason for limited capacitive drive capability.

[temperance]

The 2015 version of the LMC648x datasheet has the output impedance as figure 62. It gives some 300-400 ohm for the relevant frequencies.

Interesting. The new data sheet doesn't quote any number but states to calculate the open loop output resistance from the saturation numbers...

This is rather high if you want to drive an IXTA80N075L2 with an equivalent input capacitance of 4 nF at some reasonable speed. But of course it depends on the response time you have in mind.

Would anyone like to comment on my simplified mosfet model shown a couple posts up? Using transconductance, Ciss, Crss, and Vth from the datasheet, and the approximated Rout of the opamp, is this enough to start tuning for stability? Actually, about the Rout, shouldn't that be captured in the spice model? Do I really need to include it as extra resistance?

That seems about right with the transconductance being 12 and the values chosen for Crss, Ciss.

Edit:

Actually, about the Rout, shouldn't that be captured in the spice model? Do I really need to include it as extra resistance?

It seems the model contains Zo open loop. From the spice file: *OPEN-LOOP OUTPUT IMPEDANCE VS. FREQUENCY (Zo). What follows are some calculations and references. Maybe someone versed in reading those can make sense from that?

Source for the spice model:
https://e2e.ti.com/support/amplifiers-group/amplifiers/f/amplifiers-forum/703385/lmc6484-lmc6484-spice-model

[temperance]

Miller capacitance simulation.

If the drain voltage is constant, the capacitance seen by the driver is C_iss. In reality there is some impedance / resistance in series with the drain and the miller capacitance starts to dominate. Placing sensible source resistance / impedance values in the simulation for those is somewhat difficult and a trade off.

To be safe I would increase the source inductance towards 2 µH.

[henmill]

This is rather high if you want to drive an IXTA80N075L2 with an equivalent input capacitance of 4 nF at some reasonable speed. But of course it depends on the response time you have in mind.

So this requirement I am not sure about. For now, I don't mind having a slow response if I have guaranteed stability with the parts I have on hand. But, I have been so enlightened by this thread and others linked, that I will likely expand this design to include the pulsed current added on top of the constant current, as Jay_Diddy_B has so thoroughly documented. But first I will refine the physical design to reduce all the parasitics, and generally improve the system.

Miller capacitance simulation.

If the drain voltage is constant, the capacitance seen by the driver is C_iss. In reality there is some impedance / resistance in series with the drain and the miller capacitance starts to dominate. Placing sensible source resistance / impedance values in the simulation for those is somewhat difficult and a trade off.

To be safe I would increase the source inductance towards 2 µH.

Let me make sure I understand, you suggest I should add an inductance between the source terminal and the sense node for simulation? I do have a longish wire from the FET down to the control PCB, so that makes sense to me. And even longer wire for the return out to the front panel terminal. But everything in the control board is referenced there, so maybe it doesn't make sense to include an inductor from low side of sense R to GND.

The curve shown can not be used to get the dynamic output impedance. This is only for the required headroom. Z_out is generally higher.

The 2015 version of the LMC648x datasheet has the output impedance as figure 62. It gives some 300-400 ohm for the relevant frequencies.
The simple OP-amp models don't include the R_out part of the model. Adding the resistance gives a better model and could really make the difference.
One may still want the physical gate resistor so that the OP-amp does not oscillation - R_out of the OP-amp does not help here, it is more the reason for limited capacitive drive capability.

Understood, thank you for finding that info. I am not trying to eliminate the gate resistor, just trying to piece together a good simulation in order to find the optimal value.

The next tasks I will try to clear are:
 1) Generate Zout curve as done in reference design, but with non-inverting amp and 12V supply
 2) Follow Jay_Diddy_B's analysis for my system with Rout and my simplified model
 3) In parallel, shop for another opamp that can be had for around $2, especially if I struggle to meet stability criteria with LMC6484

I will no doubt be following up asking lots of sophomoric questions about the simulations.

Thank you all again for the help!

[temperance]

Let me make sure I understand, you suggest I should add an inductance between the source terminal and the sense node for simulation? I do have a longish wire from the FET down to the control PCB, so that makes sense to me. And even longer wire for the return out to the front panel terminal. But everything in the control board is referenced there, so maybe it doesn't make sense to include an inductor from low side of sense R to GND.

That's a misunderstanding. "source" In this context is the power source under test or V3. As such I was referring to L1 in this post by Jay_Diddy_B:
https://www.eevblog.com/forum/projects/dynamic-electronic-load-project/msg288555/#msg288555

The inductance present in the simulation is the wiring between the voltage source V3 and the drain of the MOSFET. Without the inductance, the capacitance seen by the op amp is Ciss because the drain voltage is constant. By adding L3 the miller effect comes into the picture. The voltage gain (Vds/Vgs) increases with increasing frequency as the impedance of L3 increases. The snubber takes care of keeping the gain low.

The inductance of L3 is, as I wrote a trade off. A total wiring length of 1 meter between the source under test and MOSFET drain is slightly less than 1 µH. For my taste 1 µH is not enough but this might be fine for what you envision. I would aim for 1.5...2 µH.

Breadboard wiring:
A proper solution can be a star GND construction.

-Choose a reference point. That's the GND side of the sense resistor in this case.
-Minimize the wiring length as much as possible between the source of the MOSFET and the sense resistor. (And for a high speed load you will need a low inductance resistor or a normal resistor with a snubber across the resistor or some other method to compensate the resistor inductance like an RC low pass filter.)
-All op amp related GND's go to the star GND point each with their own wire. (Reference GND, op amp GND,...)
-The GND of the source under test must also connect to this star point.
-The same goes for the snubber. The other end of the snubber must be close to the MOSFET drain.

The reference point for all measurements is also the star connection.

When not done properly, the output signal (the current in the power loop) might for example couple into the op amp inputs trough a common resistance and cause all sorts of problems because the layout problems are now amplified by the op amp.

Some people are much better at explaining this. More information can be found here:
https://www.analog.com/en/resources/analog-dialogue/studentzone/studentzone-march-2017.html

More links on the bottom of that page.

Edit: Jay_Diddy_B shared pictures of a PCB with a GND plane. You can also take a look at those.

[Jay_Diddy_B]

Hi,

In this model:



The value for the transconductance is too low.

The transconductance can be estimated from this graph on the MOSFET datasheet:




Gm = delta Id / Delta Vgs = 50A - 20A / (7V - 6V) = 30

Using a value of 30 will be pretty safe.

Jay_Diddy_B

[Jay_Diddy_B]

Hi,

If I put the MOSFET parameters into an AC model, to measure the control loop gain. I get the following result:




The simulation is showing that I have a stable control with the values shown.

Regards,

Jay_Diddy_B

 ac analysis.PNG (116.74 kB. 1912x916 - viewed 28 times.)

[Jay_Diddy_B]

Hi,

Looking at the same circuit in the time domain:





This is a very nice transient response.

Regards,

Jay_Diddy_B

[Jay_Diddy_B]

Hi,

There is a common belief that you need a lot of Gate drive in a dynamic load. This belief is wrong:



The simulation shows that less than 300uA is needed.


Jay_Diddy_B

[Jay_Diddy_B]

Hi,
and the positive edge, a similar result:





Jay_Diddy_B

[Jay_Diddy_B]

Hi,

When it comes to building the circuit, the sense resistor in the Source of the MOSFET, should be a 4-wire resistor.

The bottom Kelvin connection should be the small-signal ground for the circuit. It should be connected to the star point.





Regards,

Jay_Diddy_B

[henmill]

That's a misunderstanding. "source" In this context is the power source under test or V3. As such I was referring to L1 in this post by Jay_Diddy_B:
https://www.eevblog.com/forum/projects/dynamic-electronic-load-project/msg288555/#msg288555

The inductance present in the simulation is the wiring between the voltage source V3 and the drain of the MOSFET. Without the inductance, the capacitance seen by the op amp is Ciss because the drain voltage is constant. By adding L3 the miller effect comes into the picture. The voltage gain (Vds/Vgs) increases with increasing frequency as the impedance of L3 increases. The snubber takes care of keeping the gain low.

The inductance of L3 is, as I wrote a trade off. A total wiring length of 1 meter between the source under test and MOSFET drain is slightly less than 1 µH. For my taste 1 µH is not enough but this might be fine for what you envision. I would aim for 1.5...2 µH.

Ok, got it, yup I understand that as I've followed along Jay_Diddy_B's posts. Thank you for the detailed explanation. I am thinking of ways to reduce the inductance of the wiring inside the box. I think this will be important because I want to take advantage of the existing fans and put the heatsink(s) right in front of them. But a really compact form factor as Jay_Diddy_B presented would obviously make a lot more sense for this aspect. I'm sure the 8-10" or so of sloppy wiring and poor coupling between the pos/neg wires is adding an appreciable inductance.

See attached annotated images of the board as it is now. It could be better, but for protoboard implementation I think it's ok. I tried to beef up the traces where I had to bring in current and kept length of that path to a minimum. I also attempted kelvin connections to the two opamps sensing nodes. If I stay in this rabbit hole side project long enough, I'll probably make a proper PCB and really try to maximize the potential of the FET.

The value for the transconductance is too low.

Gm = delta Id / Delta Vgs = 50A - 20A / (7V - 6V) = 30

Using a value of 30 will be pretty safe.

Jay_Diddy_B

Oh! Thanks for the correction. I took the value 12 from this chart of g_fs, which admittedly I don't know the difference. I remember g_m from my studies, but I just saw a graph titled "Transconductance" and went for it.


THANK YOU for this quick and pointed check of my FET in simulation. Next I will ask about the non-inverting version of this for single ended supply, but I need to gather those thoughts first.

[Jay_Diddy_B]

Hi,

This shows how the value of Gm changes the control loop response:




I didn't see the Gfs curve on the datasheet, most datasheets don't have one.

Jay_Diddy_B

[temperance]

Wow, Jay_Diddy_B

extremely nice of nice of you.

About Gm. Gm at lower drain currents is in the range of 10...15. But indeed, thinking about it choosing Gm higher is safer.

There is a common belief that you need a lot of Gate drive in a dynamic load. This belief is wrong:

I would not say "wrong". It depends on the required response. The buffer I've shown places the pole created by the MOSFET driver / MOSFET Ciss much higher up in frequency and can settle in less than a few µs or even faster. An other disadvantage of a "weak" driver is poor transient rejection because the driver can't clamp the gate voltage while the control loop is lagging and while current is injected into the gate trough Cgd with some applied voltage step. The buffer I've shown has almost no overshoot because the biased PNP transistor is clamping the MOSFET gate.

The case for the voltage step is where you pre-bias the load trough a low voltage auxiliary power supply and a diode to avoid the control loop from going into saturation. But I admit this is a special case and not everyone needs such a fast control loop.

[sorin]

There is a common belief that you need a lot of Gate drive in a dynamic load.
The simulation shows that less than 300uA is needed.

First, I want to thank you for sharing your knowledge with the community here!

But, I'm not so sure about this.
For example, what happens when you connect the load to the power source?
What happens when you go from 0A to full load?
What happens when the tested power supply changes from 5V to 15V?

[henmill]

@sorin and @temperance, you are both saying the same thing, it depends on the performance requirements you need. If we are to expect to test huge load steps, seeing 10's of V/us, sure I could need a stronger gate drive. Or if I want to continuously pulse a step current like Jay_Diddy_B's dynamic load, and especially if the frequency is into the kHz. Yes I would need stronger gate drive.

For now, I will be happy to know that this version will not oscillate if I accidentally give it a strong transient. For now this will be used like a constant current load that I always ramp up slowly from zero.

If/when I get around to adding the pulsed feature, I will probably choose a different opamp and even consider a dedicated buffer stage. I'm also feeling very tempted to add some digital features like Power calculation, temperature readouts, digital current set, etc etc. We'll see.

Anywho, I've updated the AC Analysis ltspice circuit (attached), and included the power resistor, as well as return lead inductance. Also made it reflect my implementation with non-inverting amp, single supply, my opamp model etc. With the same values as Jay_Diddy_B, I am seeing what I think is very stable response. Phase margin of ~55 deg.







Let me know how else I can tune this circuit! Now I'm updating the full "mini load" sim with these parts to see the load stepping behavior.

Cheers!

[sorin]

I don't know very much about control loop design, but i think that you can not simulate a MOSFET with a current source. Especially in the case of transit response when the power varies from 0V - (to something) or when the current varies from 0A - (to something).
Tray to substitute the current source with IRFP250N, and you will see a different transit response.

Code: [Select]

.model IRFP250N VDMOS(Rg=1.44 Vto=4.0 Rd=47m Rs=0m
+Rb=5.6m Kp=13 Cgdmax=3.9n Cgdmin=0.10n Cgs=1.9n
+Cjo=1.25n Is=5p tt=186n mfg=International_Rectifier Vds=200 Ron=75m Qg=123n)

For now, I will be happy to know that this version will not oscillate if I accidentally give it a strong transient. For now this will be used like a constant current load that I always ramp up slowly from zero.

If this is the case, I would suggest you use a cheap OpAmp like LM358. Remember to avoid cross-over distortion. Or a better one is the MC34072 (only $0.3 @LCSC) which has a Capacitance Drive Capability of 10nF.  You can also use a cheap MOSFET transistor like K3878 (only $1 @LCSC). The LT1014 cost around $4.5

[henmill]

I don't know very much about control loop design, but i think that you can not simulate a MOSFET with a current source. Especially in the case of transit response when the power varies from 0V - (to something) or when the current varies from 0A - (to something).
Tray to substitute the current source with IRFP250N, and you will see a different transit response.

Others can correct me, but the small signal model of a mosfet is a voltage controlled current source. Granted, this version would not capture many of the effects transitioning into/out of different operating regions, but should capture the core function of the device.

I did it this way following along Jay_Diddy_B's guidance for another user in his Dynamic Load thread.

No kidding I'll get a different response if I use a different part. The point is to try to model my chosen part, which I am already using, as best as I can. From my limited understanding, the factor that plays the biggest part in stability is the capacitance seen at the gate. Which is complex and changes dynamically, but what I have now is a decent approximation. If IXYS provided a SPICE model, I would use it. But they do not for my chosen model.

I don't seen any advantage in switching to LM358 (really I would want 324 the quad version, but guess what they don't make it in DIP). It has similar output current limit and 100pF capacitive load drive. At a glance, the MC3407(4) looks promising, but a quick survey of suppliers says the quad version in DIP is not in stock anywhere.

The goal here is to gain confidence that I can use the parts I have already with the right compensation. So far, it's looking like it is not impossible. Though if I could go back in time, I might have chosen a different opamp for this purpose. I am using a spare that I have on hand for a different project.

One of the primary goals of this project is to spend as little money as possible on it! I am not going to buy a new opamp unless I absolutely have to. And I'm definitely not going to sub out my linear FET.

It seems these aspects of the project keep getting forgotten by some on here..

[Kleinstein]

The DIP version of the LM324 would be no issue. For the MC34074 it looks like there was never a DIP version.
The main point is getting an OP-amp that is single supply and thus can work down to the negative supply.
Another option, a bit similar to the MC34074 is the TLC274.
I don't see a need for quad OP-amp - only 2 of the amplifiers are critical. As dual there is the LT1013 as a version with good accuracy, if this is wanted.

[temperance]

If an LM358 fits your application depends. The offset current= op amp offset voltage / Rsense or 20 mA for 2 mV offset with a 0R1 sense resistor.

The model is fine. Unlike your MOSFET model, transconductance is non linear in a real MOSFET. But you've set Gm to be 30. Anything lower than 30 will only improve phase margin because the MOSFET voltage gain decreases. It is anyhow a trade off because the voltage gain depends on the wiring inductance and the snubber.

Crss dependen on Vds. You could try higher values for Crss as the value of 325 pF applies for Vds= 20 V. Crss is 700 pF with Vds is 5 V and 1 nF at 2.5 V Vds. (Crss is taken from Fig.11 from the data sheet) I think this is more realistic.

You've modeled two inductors in series with the supply under test. This is not required as the supply under test can be replaced by a short for AC signals (up to some frequency in real life).

[Jay_Diddy_B]

Hi,

The LT1014 is really a trimmed version of an LM324.


From the ADI (Linear Technology) datasheet:

The LT®1014 is the first precision quad operational amplifier
which directly upgrades designs in the industry standard
14-pin DIP LM324/LM348/OP-11/4156 pin configuration.
It is no longer necessary to compromise specifications,
while saving board space and cost, as compared to single
operational amplifiers



The main feature is reduced input-offset voltage.

The other features that are common to between the LM324 and LT1014

The common mode input includes ground and the output can swing close to ground. By ground it means the negative supply voltage in single-supply applications.

The datasheet says:

 Both the LT1013 and LT1014 can be operated off a single
5V power supply: input common mode range includes
ground; the output can also swing to within a few millivolts
of ground. Crossover distortion, so apparent on previous
single-supply designs, is eliminated. A full set of specifications
is provided with ±15V and single 5V supplies


The LT1013 is a better LM358

and the LT1014 is a better LM324

The LTspice library does not include the LM358 and LM324. The LT1013 is a suitable substitute.


In the Jay_Diddy_B original design I used dual power supplies, +/-9V. I did this to make summing of the static reference and the dynamic reference easier. The dual-supply allowed me to use a wide range of op-amps that don't need include the negative supply rail in their input common mode range.


Jay_Diddy_B

[Jay_Diddy_B]

Hi group,

I am going to explore buffering the output of the op-amp using LTspice models. You can decide if the extra complexity is worth the results.

I replaced the transconductance model of the MOSFET with a real MOSFET model.

Unbuffered





Ideal Buffer

The voltage-controlled voltage source E1 has a gain of 1.



Practical Buffer - 4 BJTs - Diamond Buffer

This is based on the circuit of the National Semiconductor LH002



Regards,

Jay_Diddy_B

[henmill]

The DIP version of the LM324 would be no issue. For the MC34074 it looks like there was never a DIP version.
The main point is getting an OP-amp that is single supply and thus can work down to the negative supply.
Another option, a bit similar to the MC34074 is the TLC274.
I don't see a need for quad OP-amp - only 2 of the amplifiers are critical. As dual there is the LT1013 as a version with good accuracy, if this is wanted.

Thanks, I guess I was mistaken on the M340xx. Anyhow, if I feel the need to buy a new one I will likely start with the Digikey filter and work from there. Sometimes it's easier to start by filtering out what is available and in my price range, package, etc. TLC274 looks nice.

I mostly want a quad to keep my current board going, maybe make a new one but in the same style. I need one amp for buffered reference, one for the gate, and another for panel meter. The 4th I want available in case I implement some kind of overcurrent detection/prevention. Or I could have a second FET for more power. Etc.

If an LM358 fits your application depends. The offset current= op amp offset voltage / Rsense or 20 mA for 2 mV offset with a 0R1 sense resistor.

The model is fine. Unlike your MOSFET model, transconductance is non linear in a real MOSFET. But you've set Gm to be 30. Anything lower than 30 will only improve phase margin because the MOSFET voltage gain decreases. It is anyhow a trade off because the voltage gain depends on the wiring inductance and the snubber.

Crss dependen on Vds. You could try higher values for Crss as the value of 325 pF applies for Vds= 20 V. Crss is 700 pF with Vds is 5 V and 1 nF at 2.5 V Vds. (Crss is taken from Fig.11 from the data sheet) I think this is more realistic.

You've modeled two inductors in series with the supply under test. This is not required as the supply under test can be replaced by a short for AC signals (up to some frequency in real life).

Thank you for pointing out the Crss behavior, I will definitely step through some values and see how performance changes.

About the inductor in series with the DUT return, I thought it just made sense if we were including it on the positive side. Often times a source will be hooked up with longish leads that aren't well coupled.

Or is it that there is just no interaction with the stray inductance beyond the control's reference? So it doesn't matter for the control stability? (thanks for helping my understanding in advance)

[henmill]

Hi everyone,

Sorry for the extended lack of updates. Lost some steam via lack of free time, but I also detoured to rework the thermals and layout of the system to get it to it's temporary final state so I can get back to other work.

Recently I've spent an embarrassing amount of time dinking with the sims, but realized a mistake the other day that has unlocked my ability to move forward

Earlier in this thread I said one goal of the project was to use as much of what I have on hand and spend as little as possible. But I was lacking capacitor values between 200p and 10n, and also wanted some NTCs to incorporate, so I also shopped around and ordered some LM324 and TLV2374, just in case I have problems with the LMC6484. I still don't want to sink much $ into this project, but I will take any excuse to enhance my library of parts haha.

So, starting with the new thermal/layout concept:

I switched to a short, wide, finned heatsink, mostly because the other one I could not quite fit comfortably enough to close the lid. Not sure if this new sink is optimal but I would think I could dissipate 50W continuously. I need to do more research to back that claim up though, but will likely just test it empirically





Now, onto the simulations. I've done some comparisons between the LMC6484 and TLV2374 with the simplified small signal model of my part IXTH80N075L2, as well as the model provided for a different IXYS part, used by a different user that Jay_Diddy_B also helped out. That part number is IXTN4650L, and you will notice it has even higher apparent capacitance Ciss compared to my part. So to me a reasonable hypothesis is that if my configuration is stable driving either part, there is a good chance it will be IRL.

In addition, I ran the simulation at Vin of 5V and 25V, and adjusted my model based on the datasheet values of Ciss, Crss vs. VDS:


To summarize, attached are sims showing phase margin for the following:

opamp     |     Mosfet     |     VDS     
LMC6484  | IHXTH80N.. |    5V
LMC6484  | IHXTH80N.. |    25V
LMC6484  | IHXTN46N.. |    5V
LMC6484  | IHXTN46N.. |    25V
TLV2374   | IHXTH80N.. |    5V
TLV2374   | IHXTH80N.. |    25V
TLV2374   | IHXTN46N.. |    5V
TLV2374   | IHXTN46N.. |    25V

Long story short, I think I am safe to use the LMC6484, but might swap it out anyways to save it for something where its features can shine more. Please let me know any thoughts you have regarding my methodology and reasoning!

I will get around to running transient sims eventually...

Here is the schematic used for all these, in which I swapped the opamp and mosfet around to compare.


Another detail, I have decided to ditch the idea of using a big power resistor in series. With the parts I have, even at 1 ohm resistance I will be limiting my testable current to 5A at 5V (at best!) and I would like to have the ability to sink more at the low voltages, just in case! If anything, I might rig up a disconnect with overcurrent trip, or a plain old regular fuse.

There is probably more I could say, but I want to get this out here for comment.

Thanks as always for feedback!

[henmill]

(Continued due to attachment limit)

Here is the schematic showing the other mosfet in use:

[RoGeorge]

You may want to read about "ako" (a kind of) feature in LTspice.
https://ltwiki.org/index.php?title=Undocumented_LTspice

"ako" is very useful when comparing the outcome of running the same schematic with different parts, so you won't have to compare them manually.  LTspice can ".step" the model of a component just the same as you ".step" the value of a parameter, and can show them all on the same plot.

Same for the phase margin.  You write a ".meas" to find the phase margin, define ako models for each op amp type (or for each MOSFET type), then .step the .ac simulation.  Then look at the log file (usually opens with CTRL+L) to see the values of the phase margins for all the op amp you stepped through.

[henmill]

Thank you for the tip! That does sound much more efficient than what I've done to this point. It was a bit tedious running and re-running making sure I've got the differences right.

[Jay_Diddy_B]

Hi,

Here is a much faster model. I used the SPICE model for the MOSFET from Littelfuse. I could not find the exact part, so I used another similar part:



The SPICE model is pasted on the schematic. If you do this you don't need the .lib directive and the .asc file is self contained.

This runs in the frequency domain.

After running the model plot V(a)/V(b) to get the loop gain.


I have attached the model.

I used an op-amp from the LTspice library.

Regards,

Jay_Diddy_B

 IXTH30N60L2 version.JPG (112.98 kB. 1456x730 - viewed 23 times.)

[Jay_Diddy_B]

Hi,
With the faster model you try things easily. Here is an more optimized circuit, for this MOSFET:



Regards,

Jay_Diddy_B

[Jay_Diddy_B]

Hi,

You can check the time domain too:





Note: I have been playing with the component values.

Jay_Diddy_B

[henmill]

@Jay_Diddy_B,

Thanks for providing the quicker way to find phase margin! This helps immensely with my trial and error circuit design haha.

I'm having some trouble running a transient sim for some reason though. Would you mind providing the settings you used? Can't see them in the screen shots.

I've attached mine for reference. I set V2 to be a square wave, but it's like it stops evaluating after a short time.

EDIT: I think the problem was starting voltage set to 0. If I give it a small value like 10mV, it works as expected. Seeing lots of overshoot and ringing with the values provided, will update when I get something with cleaner edges like your examples.

Thanks!

[henmill]

Hi folks,

After playing with values in the transient simulation, I've come up with a configuration that looks ok both from AC analysis and stepping the current setpoint in the time domain.

But I still have the issue that I don't have the "right" model to match my part. I reached out to Littelfuse last week asking for a model, but I'm not holding my breath that they will provide it.

I optimized values around the IXTH30N60L2, but if I try substituting in the simplified model of my part, the transient became very difficult to get under control and I end up with some way different values compared to using a "real" spice model of the different FETs. I have a feeling the simplified model is just not quite valid for this type of analysis.

So I welcome suggestions from the group: would you recommend using the values found using the IXTH30N60L2 (much higher gate capacitance) and just perform some tests with the real hardware and adjust as necessary?

I'm imagining one test I can try is to set the load current at a few amps, turn on my power supply, and hot plug it in to see if it can settle without oscillating (watching on the scope). I will be wearing safety goggles for this haha.

Since I don't have the pulsed current feature yet, this is one scenario I could feasibly encounter that could cause the system to lose stability.

Anyhow, attached are some sims showing the disparity in component values between the real spice model and the simplified current source model.

edit: I should say for the simplified version showing the phase margin, you can see the gain peaking and in transient with those values, there was massive ringing on the rising edges. I did not get a screenshot but that is the reason for the big change in values in the transient sim that followed.

[Kleinstein]

So far the simulation shows a lot of phase resere and the unity loop gain well in the 90 degree zone. So a very conservative compensation.
There is quite a hefty RC snubber at the output. Normally one would want to get away with higher impedance there, e.g. ideally < 1 µF and more resistance.


To see the effect of different source impedance on can do an AC simulation with an AC source at the output (V3). This would simulate the output impedance / conductance. This would tell how much snubber is really needed.

[henmill]

Thanks Kleinstein.

The reason I have the 1R + 5.7uF snubber is because that is what I have built. I have all these big beefy 1 ohm resistors and due to their size I didn't feel like wiring 2 or more in series. And with simulation I (at least thought) I was getting better results with slightly higher cap values in combination with the 1 ohm.

Do you think it would be better to start with 1R + 1uF and go from there? It is easy for me to remove the 4.7uF cap I have in parallel with a 1uF.

I will add some 2 ohm resistors to my digikey cart to round out my options.

Here is a picture of the snubber with sense resistor (0.2R || 0.2R) as I plan to have it built. I meant to post this with the last reply.

[henmill]

I finally got around to turning this thing on again.

I decided to pick some values and hold my breath and see what happens. Rather than list them out, here is a schematic view showing the nominal values of what I have on the board today:
edit: maybe it goes without saying if you've been reading, but this schematic does not show my actual FET part number.


At a glance, it is functional at least. I didn't have much time tonight but I probed around a bit and ran a couple quick tests.

First, I just wanted to watch the sense node and gate to look for any weirdness. Perhaps I found something of interest, but I'm guessing it might be the ripple from the power supply "under test".

In the waveforms, channel 1 (yellow) is the sense node/Source.

In this waveform, the setup was running at 15V in, 2A. Channel 1 is AC coupled and you can see the sawtooth shape at the sense node. Channel 2 (blue) is the gate. It seemed steady enough, though maybe I should have looked more closely to see if the same frequency is present at the gate. 35mV pk-pk doesn't seem like much, but when a 1A set current should be 100mV, that is quite a deviation. The amplitude seemed about constant as I moved up and down in current.


I decided to get crazy and try a quick "hot plug" test at 10V 1A. In this capture ch1 is the sense node and ch2 is at the Drain. For this test I had the unit running at 10V, 1A. Then I disabled the power supply and unplugged the + wire. Then I turned on the power supply output and plugged it in.


Here are also a couple pictures of the hardware.

Thanks as always for feedback, and if anyone wants to suggest a test plan, I'd welcome it!

[RoGeorge]

Nice build! 

(May I kindly ask you next time to embed inside the text full size pictures, please, and not their thumbnail, because the thumbnail opens in a new tab, so it's bamboozling to go back and forth between the text and the picture tabs.)