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Laser Diode driver - kHz modulation & 1% duty cycles

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smoothVTer:
Hello Everybody

I've been working with laser diodes most recently and have been able to come up with an almost-working design, albeit with some significant hurdles I have yet to overcome. Basically, I cannot get the transient response I am looking for when PWMing at a few kHz and going to very low duty cycles.   Submitting here to get your expert advice.  First, the schematic:



The theory of operation:   When a current flows through the LD, a reverse current proportional to the light output is generated through the PD.  The LD and PD are in the same 3-pin package ( this being an N-type LD )   Rpd converts this reverse current into a feedback voltage.   The OPA's inverting input is connected to this feedback point. The OPA non-inverting input is connected to a 10-bit DAC which I can digitally control through the MCU.  Therefore, this DAC sets the peak LD current/optical power.  The OPA drives enough current through Q1's base in order to achieve the requested peak voltage at the Rpd point.

The LD I am using are all either IR or red LD's.   Their monitor photodiode current can varying wildly:  I've seen as low as 50uA all the way to 250uA for the same optical output power using LD's from the same box.   

Now in order to achieve varying optical powers, I utilize PWM and vary the duty cycle of a special feature of this OPA.   This particular OPA can switch its output pin within 50ns between (a) actively driven and (b) high-Z      When driving, the OPA servos current to Q1's base and ramps to/holds the peak laser power.  When in high-Z, Rbe removes base charge and quickly puts Q1 into cutoff.   

The Vref, DAC, and OPA are all actually integrated onto a single die along with the MCU itself.  For reference, it is a PIC16F17** series MCU.   The OPA has a 3.5MHz GBWP, 40 degree phase margin, 3V/us slew rate, a common-mode range of 0-VDD and an open-loop gain of 90dB.  I'm running this MCU and thus this OPA at 3.3V.   For reasons I cannot get into here, I am more or less forced to use an integrated approach like this rather than a separate OPA, MCU, DAC, etc.

About the feedback network:   I had to really wing this part of the design and just solder and unsolder caps until I got a somewhat workable response.  Cf1:  anything below 3.3nF and the base drive oscillates wildly.  I finally settled on Cf1 = 10nF and get somewhat stable results.   Cf2 and Rf are currently just placeholders, to be used if I can figure out how to properly do Type II compensation.   I am not sure how I would calculate this beforehand. 

Q1 is a 2SD1979GSL  NPN.   I have several other NPN's on hand I've been experimenting with.  The best results I've found are with NPNs that have a high hfe  and a lower ft range.   I tried originally using several MOSFETs in this scheme, but all of them horribly oscillated and I could not get anywhere near a flat response with any NMOS I tried here.   Probably had to do with the OPA's ability to drive a capacitive load.

Now, some scope images to illustrate my problem:



YELLOW trace is the feedback voltage at Rpd.  GREEN trace is the voltage on Q1's base.  PURPLE trace is the LD Anode ( the LD_SUPPLY )   RED trace is the LD cathode.   LIGHT PINK trace is  (LDA - LDK) for a differential measurement from LDA-LDK, giving me an idea of the LD forward voltage.   Here, I have the PWM frequency set to 4kHz and illustrated is a 5% duty cycle.  I start with the DAC set to something very small, like 100mV.  Then I adjust the DAC output upwards until I can trigger on the edge of the Rpd feedback signal in YELLOW. 

I see a rather fast ramp up with significant overshoot on the Rpd signal.  Not sure why that occurs here. 

Also, I see a rather fast ramp up to ~500mV on the base drive as soon as the PWM signal goes high and ... but then a slow and steady linearly increasing ramp of the base voltage until finally it flattens out.  It is this slow and steady ramp up of Vbe that hinders low duty cycles.   A zoomed in scope shot:



Upon the PWM signal going high/OPA driving, the base voltage shoots up quickly to about 500mV -- below threshold -- and then slooooooowwllly ramps up as you can see in the above scope shot.  This is a 5% duty cycle ON pulse shown.   If I go to 1% duty cycle, the entirety of the ON PWM signal is spent in this slow ramp-up, which keeps Vbe below threshold the entire time, effectively giving me zero output on the LD.    When this happens surprisingly, I still get a photocurrent feedback signal, which I don't understand at all.  If there is no lasing action, there should not be any feedback signal ...

I'm hoping to gather insight into the following points:

(1)  Is there anything in this circuit that strikes you as faulty or terribly incorrect?  Are any of my assumptions flawed or incorrect?
(2) Is there a better way to go about compensating this OPA for a better transient response and reduce the ringing on the rising edge?  Can I do this empirically as before?  I do not have access to a VNA to do fancy stuff like the loop gain/phase measurement ... 
(3) Why does the OPA seem to quickly slew to 500mV, but then exhibit that slow ramp-up to threshold?
(4) Can this integrated OPA do what I am asking of it, given its GBWP and slew rate?   
(5) Any other ways to improve this circuit by adding or deleted external elements?
(6) Would an NMOS work better here, if I were somehow able to get the circuit to not oscillate?
(7) Eventually I would like to get this circuit to work up to 10kHz modulation rates with 1% min duty cycles.  Would that be possible given this OPA? 

Thanks for reading! 

janoc:
Well, this is a bit outside of my field of experience but I have a hunch that the opamp in the PIC is not designed to be abused like this. It is  a very slow opamp - 3V/us slew rate is not stellar and this will directly affect the current ramp-up. If I see correctly, your scope captures are at 20us/division, so that ramp-up seems to pretty much match the declared slew rate of your opamp.

The other thing is that as soon as you turn the laser on, the photodiode is doing negative feedback and is acting against the rise of the current.

The fast rise/overshoot may be spurious and due to your probing (parasitic inductance of the wires).


Also who knows how the opamp output behaves when you are turning the pin driver on and off (well, on and high-z). That's not normally the way PWM is done and the PIC pin drivers may not like that too much.

I would probably prototype this first by using a discrete opamp and a signal generator, just to make sure that the rest of the design isn't doing something weird before messing with the PIC.

adamcord:

--- Quote ---(3) Why does the OPA seem to quickly slew to 500mV, but then exhibit that slow ramp-up to threshold?
--- End quote ---
The way you have the OPA configured, with a feedback capacitor, is like an integrator, which is my guess as to why it shows that ramping behavior. Can you probe the output of the OPA before the 330 Ohm resistor? I would expect that to look like a ramp.

StillTrying:
A nice long post, but too much for me to digest in one meal. :)

I don't think the first bit of your yellow PD signal is the PD, I think it's the op amp's output rising when enabled, and 'the ramp' is CF1 discharging. then the op amp 'works'.

The PWM plus DAC control seems complicated, especially as it's the opamp's output which is switched on and off.

 

smoothVTer:
I think you're right about the photodiode ...

To make sure my LD/PD is still good, I took the LD/PD device out of its mount and into a LD controller to measure the photocurrent.  Then I forgot to put it back in circuit, and powered up everything with probes in place.  Surprisingly the yellow trace remains the same ... in the total absence of the photodiode current!  How does this make sense?  There is no DC path from OPA OUT  to OPA -IN  ... I don't understand how this could happen.

 

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