Logic "fan in" - multiple outputs, single input

[TomS_]

I was just reading through the Wikipedia article about 4000 series logic, and clicked through to an article about fanout (https://en.wikipedia.org/wiki/Fan-out) and I came across something which caught my attention.

Specifically this:

no logic gate input can be fed by more than one output

Ive designed a nice little compact circuit using 4 logic gate chips (with 2 gates to spare) which I was quite proud to achieve, but I have a small section of circuit where I combine 4 outputs into a single net and feed them all in to a single input on another gate.

Based on the above, it sounds like I'll need to add a 5th chip with perhaps a quad input OR gate to take all 4 outputs and produe a single output?

But why is it that multiple outputs cant be fed in to a single input?

[MK14]

If you connected up multiple outputs together, and some of them decided to produce a logic 1, and others a logic 0. They would electrically fight each other (a bit like a short circuit), potentially overloading the chip(s) and maybe even damaging them.

There are outputs called "tristate" or "open collector", which can solve this problem. Tristate can be switched off (disabled), so that things can share, often called databuses e.g. for memory.
Open collector means that the outputs can only pull things towards ground, so it does not matter if you connect multiple outputs of that type, together. But it needs a (usually single) pull up resistor.

You did the right thing. The OR gate is the way to go.

[TomS_]

They would electrically fight each other (a bit like a short circuit)

Ahhh right...

Now that I look a bit more carefully at the datasheet for one particular CMOS device, e.g. a 4071, the output is configured as a totem pole with a P and N junction FET, so when high it sources current, but when low it sinks it. So yes, potential short circuit conditions, and I guess additional OR gate(s) it is!

Makes a lot more sense now. Thanks! 

[technix]

There are situations where multiple outputs can be connected together in an orderly fashion without a short happening:

1. Open-drain outputs don't have the PMOS on the top, and rely on a pull-up resistor instead. This results in a wire-AND situation.

2. Tristate outputs with chip select. Tristate output can emit a High-Z state which neither FET turns on. This releases the line and allows someone else to drive the line. A chip select line is often included to allow arbitration deciding who get to drive the line.

These are common ways buses are constructed. An example of open-drain bus is I2C. An example of tristate bus is SPI.

[bson]

You can also wire up multiple outputs in parallel for higher current capacity.  Just make sure they always operate in lockstep.