SPI isolator and stuck MISO line

[shraken]

Hello EEVblog members: first time poster but long time reader!

I've been doing some work with digital isolators from Analog Device's line designed to support moderate data rate SPI communication.  Specifically, I've been using the ADUM3481. 

I've gotten the ADUM3481 to work with my SPI devices using the AD3481 EVK and my my own PCB w/ the digital isolator. 

The problem I'm having is when I attempt to add multiple digital isolators I find the MISO line gets stuck.  I found a forum post on AD where someone else describes similiar issue.  I've attached block diagram of my setup:


https://ez.analog.com/message/138840

Basically, the digital isolator has no conception of high impedance/open-drain so the MISO line will always be actively driven high or low.  I tried implementing the recommended circuit from the above post to correct this, block diagram below.  I used a 1N4148 (0.5V drop) placed in series from the isolators SOMI output to the SPI master MISO line.  I made the SPI master MISO line common with the diode cathodes.  With this configuration I got garbled data on the MISO line and wasn't able to cleanly read-out either device. I then put in pull-down resistors on the diode-OR (68k) network which allowed one device to work but other device wouldn't now.  Am I doing something obviously wrong here?  Is the forward voltage drop of the diode too large (should I try to use an ideal diode or a Schottky instead of PN?). 



Has anyone done this before?  Is this the recommended approach w/ regard to isolation and signal lines that require high impedance?  Would it be better to have a single digital isolator and break the isolated MISO line to each slave?  The later approach is often challenging given constraints on wiring, etc.

Looking forward to any feedback or helpful advice here.  Sorry this question might be a bit detailed, I thought about sharing on electronics.stackexchange too

[Marco]

My guess, the resistor is too large ... you could easily have 10s of pF of capacitance, with 68k that gets you microsecond RC times, likely too slow. The isolator has output current limit value of 10 mA, try 1K. An alternative is a real OR gate.

PS. what I/O voltage are you using?

PPS. oops, I just realize you need pull downs on all the slave sides ... the voltages there are undefined when they are high impedance.

[shraken]

Hi Marco, thanks for responding!

I/O voltage is 3.3 Volts.

SPI clock speed is 100 kHz with fairly fast edges (100nsec).

I lowered resistance from 68k to 4.7k and was able to communicate with both slaves but was still occasionally get a stuck high bus as my A/D counts would be 0xFF 0xFF.  I then lowered resistance further to 1k but problem actually just got worse with 0xFF 0xFF counts. 

[Marco]

As I said, the MISO pins on the slave sides need to be pulled down too.

[Ian.M]

Why not simply use a single gate non-inverting tristate buffer with active low enable on each isolator's MISO line with their /EN pins driven from the /CS line going to the same isolator?

[lovro]

You could use a OR circuit with diodes or a tristate buffer or some other circuit, but it is probably the best just to use another ADUM like the ADUM240x it has an enable pin. 

[tszaboo]

Hi Marco, thanks for responding!

I/O voltage is 3.3 Volts.

SPI clock speed is 100 kHz with fairly fast edges (100nsec).

I lowered resistance from 68k to 4.7k and was able to communicate with both slaves but was still occasionally get a stuck high bus as my A/D counts would be 0xFF 0xFF.  I then lowered resistance further to 1k but problem actually just got worse with 0xFF 0xFF counts.

The diode logic was a thing in the 1960s. I dont understand why arent you using a tristate buffer with the enable line, FET switches, digital multiplexer or anything which is recommended by 21 century digital logic.

[Ian.M]

Unfortunately the ADUM240x series enable pins are active high.

[shraken]

As I said, the MISO pins on the slave sides need to be pulled down too.

Hi Marco:

Sorry, I had missed your edit before, indeed -- needed pull-down on the isolated MISO signals to avoid weird float condition being translated back to the MCU SOMI signal.

Very much appreciate the assistance!

Ian.M/NANDBlog: indeed a tristate buffer with active low control tied to chip select is fine solution.  I was doing bit of re-work on existing board so grabbing two-terminal diode seemed liked quickest route (ordering supply of tristates and diodes now to replenish). 

lovro: solid recommendation ont the ADUM240x series.  Not a huge deal with an inverter, might do something like this in future maybe.