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| Level-translate the output of a TCXO crystal oscillator module |
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| pigrew:
I'm working on nearly the same circuit, and am equally confused. I've seen two classes of designs: (1) The oscillator manufacturers suggest using an inverter with a large resistor as feedback. Some split the resistor into two halves and add a filter capacitor to ground between them, providing a more stable load to the XO. (2) Others use a high-speed comparator. For example the HP 33120A and 33220A frequency reference inputs do this. I don't know about other instruments. For my use, low jitter is not important, so I'll use an inverter with feedback. The different between the datasheet (V_IH - V_IL) isn't so important, and does not need to be more than the peak-peak of the input. This is because the inverter actually has a very small (V_IH - V_IL). The datasheet's values are guard-bands due to process and temperature variation. This website from Johns Hopkins has a nice image showing the threshold voltage variation of different devices. The inverter in the circuit will self-bias to hold the input at very close to the threshold voltage of the inverter with the 0.8 Vpk-pk input being larger than the actual (V_IH-V_IL) of the inverter. Note that Schmitt trigger inverters should not be use since they have hysteresis often > 1V. Comparators with Schmitt trigers are reasonable since they usually have hysteresis much less than the input's pk-pk voltage. |
| floobydust:
Here is what worked for me. The VCTXO oscillator module outputs a "clipped sine wave, DC-cut, 0.8Vpp" which means AC coupled output. The module has an internal coupling capacitor in series with the output, so I used a DC-biased Schmitt trigger to square it up. It all runs off 3V and enough drive for the 5V counter. |
| David Hess:
Phase noise usually does not matter and may actually desirable in frequency counter gate timing to prevent synchronization. The simple data slicer configuration of a comparator will adapt a poorly controlled input into a pulse output. This might be desirable if you do not want the output duty cycle varying too much. Single gate amplifiers have very poor power supply rejection but are usually free. Technically I guess you are suppose to use an unbuffered gate but I have never had problems with HC logic in this application. Maybe faster CMOS logic would be a problem. |
| pigrew:
--- Quote from: floobydust on May 19, 2018, 06:43:43 am ---Here is what worked for me. The VCTXO oscillator module outputs a "clipped sine wave, DC-cut, 0.8Vpp" which means AC coupled output. The module has an internal coupling capacitor in series with the output, so I used a DC-biased Schmitt trigger to square it up. It all runs off 3V and enough drive for the 5V counter. --- End quote --- Thanks for posting your schematic. My application is to interface with 5V logic, so I have to use a different logic family. Based on David Hess's comment, perhaps I should have used an unbuffered inverter. I already ordered a buffered inverter, but in the future I think I would use the SN74LVC1GX04 which you mentioned above. I'm confused about the "10kohm || 10pF" +/- 10% specified in the datasheet. I interpret that as a requirement of a 10k load, or else bad things may happen. However, all of the schematics I found (google image search) show only a 510k or 1 Mohm load resistor, so maybe it doesn't matter so much in practice. Your schematic shows a 5 kohm load, so perhaps it's overstressing the TCXO. I'm attaching my current circuit layout. I changed one of the feedback resistors to 10kohm to try to present the proper load. I'm guessing that the capacitance is close to the desired value (the inverter is ~6 pF, plus a bit of parasitics throughout the board). Based on simulations, the circuit reaches equilibrium after about 5 ms. |
| floobydust:
At work, these osc modules they were throwing out in the garbage, so this is why I used it. Inside the VTXCO, a 10MHz crystal, COB IC and series output capacitor. In all likelyhood, it's just 4049UBE stages for the oscillator and output. I did not see the output amplitude drop with 5k ohm load, so I left it alone. It's not the raw crystal oscillator but rather an analog buffered output. When I used unbuffered gate(s) the amplitude went up but still a sinewave with slow enough edges and I got chatter in the counter's input gate. Then I decided to use a Schmitt trigger to square it up. At some point, the sine to square conversion has to take place. I wondered if your circuit might not work due to the osc module's output impedance? I think if it's low (<<10k), R2 may not do anything. |
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