EEVblog Electronics Community Forum
Electronics => Projects, Designs, and Technical Stuff => Topic started by: TaylorD93 on September 02, 2022, 10:02:58 pm
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Evening all,
Ive had this week off work so decided to have a play about and to try and cobble together a linear PSU. No exact purpose intended but i wanted to build one and thought, why not?
I wouldnt count this as a success by any stretch of the imagination. I wanted to build a PSU using discrete components i.e. BJT, Zeners and basic passives. Im not quite sure where i went wrong with the design, it started out as scraps of paper and i cobbled it together with the parts i have either from old salvaged parts or new parts i keep stocked.
I have made some leaps in my design assumptions which may have sent be down the wrong path to start with, but i was looking to have a fixed output PSU with approx 1.1A of output current with current foldback protection. Again, this was to built with parts i already had so that did influence alot of my choices, and i didnt want to just pop in an LM317 as i wanted more of a learning experience ;)
Design
I started off with the transformer, its an old toroidal salvaged from the scrap bin at work, it is rated at 2x25VA 18VAC windings, with a 13% load regulation. It has a 230VAC input, but in the UK mains is rated at +10%/-6%, so i would expect the output to vary from a minimum (full load at -6% input) 16.9VAC up to 22.43VAC (No Load at +10% Input) Both secondaries were to be connected in parallel.
With an estimated 1.3A load current, i worked out an approximate ripple voltage of 3V pk to pk with a bulk capacitance of 4400uF (Vripple = Iload / 2*F*C)
After the Vf of two diodes, plus this ripple, it gave me a worst case input voltage of between 19.5VDC upto 30.5VDC. As 30V is a bit high for an opamp supply rail, this was another reason to keep it discrete.
The idea is that R1, R2 and D5 provide a 5.1V reference voltage, this combined with Q1 and R3 should give a constant current sink of 4.5V / 390 Ohms = 11.5mA. This then provides a sink reference current for Q2, Q3 and Q4 which are a PNP current mirror circuit.
Q3 simply should provide a current limited source for the Power On LED.
Q4 provides a source for the pass transistor circuits.
Q5, Q6 and Q7 are the pass transistors, Q6 & Q7 are on a common heatsink, Q5 was not (but on its own smaller one)
Q8 should "fold back" the output when an over current condition occurs, switching on the Over Current LED (LED2) as well as sinking the source current from Q4. This is determined by the R8/R9 and R10 network.
Q9, Q10 and D6 provide the feedback for regulating the output combined with the resistor divider network etc.
F2, the output fuse, should never actually blow, its only there if there is a reverse polarity connection (say to a battery) in which case D7 conductors and blows the 2A fuse.
Testing
Now as good or as bad as all that is, i built it and powered it up with a bench psu (F1 not fitted, DC applied to the fuse terminal), with 20V input (approx 19.4V at the C1/C2) it initially seemed ok but did have issues.
R4 was getting very hot. Im not quite sure why, it may be due to the output impedance of Q3, but i was essentially getting 35mA through R4 and LED1, so i bumped the 330R upto 1.8k and it was closer to the 11mA target figure. So i continued
I connected up a Load, and it was regulating ok at 13.8VDC output, i ramped up the load and it did regulate it upto about 1.1A when the current limit started to kick in. At this point the "foldback" circuit didnt work too well, it still allowed 1.3A to flow through the load, so it didnt "fold back" just current limited.
I removed the load, and it regulated back to 14.5V (not ideal) but i appreciate this is all down to the thermal drift i had just introduced by heavily loading the circuit. It soon drifted back down to 13.8VDC as the thermals cooled down. I think if i had use an Opamp for the feedback/regulation circuit, this would have been less pronounced as the higher gain would give much better regulation, providing the voltage reference was thermally stable.
Now with some degree of confidence, i raised the input voltage to 30VDC. Switched it on, and after a split second it suddenly died. With no load on the output, Q10 and D6 both burnt up and let the magic smoke out. This bit i do not understand.
Assuming 11mA from Q4, with no load, the maximum the Collector of Q9/Q10 should be is approximately 15VDC, even if Q10 was sinking all of that current, the max it should have been dissipating was only 110mW, and D6 56mW.
So my initial thought are either Q4 was not sourcing a mere 11mA as i assumed (possibly indicated by the LED current with Q3) or i have made a severe under estimation at the power dissipation of Q9/Q10 and D6.
I might try changing Q10 for a BD237 as it has a bit more power dissipation. But i dont think that is a particularly elegant fix and is more of a brute force/sledge hammer. Perhaps also try and rework the Current mirror circuit, although im not completely sure how to do that at this time.
Any thoughts/comments or scores out of 10 welcomed,
thank you for taking the time to read my post,
Taylor
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A current mirror with discrete transistors is tricky. It may work, but it may also get unstable as the hotter transistor tends to get more current. With discrete transitors one should add emitter resistors to get more stable currents.
25 VA at 18 V is barely 1.4 A. The rectifier plus filter cap combination results in the AC current to be higher than the DC output. With a large transformer this may be a factor of some 1.5 to 2. With a relatively small transformer it tends to be a little better, but usually not that much. So 1.3 A DC would overload the transformer.
The drop on the R8 shunt for the current limit is quite high and thus lots of heat there. It may be just acceptabe for a short, but not really practical when high voltage.
With so much series resistance and the output capacitor the circuit may actually oscillate.
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A current mirror with discrete transistors is tricky. It may work, but it may also get unstable as the hotter transistor tends to get more current. With discrete transitors one should add emitter resistors to get more stable currents.
25 VA at 18 V is barely 1.4 A. The rectifier plus filter cap combination results in the AC current to be higher than the DC output. With a large transformer this may be a factor of some 1.5 to 2. With a relatively small transformer it tends to be a little better, but usually not that much. So 1.3 A DC would overload the transformer.
The drop on the R8 shunt for the current limit is quite high and thus lots of heat there. It may be just acceptabe for a short, but not really practical when high voltage.
With so much series resistance and the output capacitor the circuit may actually oscillate.
Ill look into adding the emitter resistors.
The transformer VA rating is 2x 25VA so i have a factor of 2 on the DC load current vs AC current rating. As both secondaries are in parallel i get 18V 2.8A
R8 is its value to provide enough volt drop to help trigger the R9/R10/Q8 foldback circuit. But as that doesnt seem to be working anyway i need to work on improving that too.
Thanks for the feedback :)
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Hmm, very old fashioned, simple design for the most part.
Yeah 10mA is WAY too much for a discrete, un-balanced mirror at 24VDC. Consider the effect of its dissipation: 240mW or so will raise its temperature significantly (~40C?), reducing Vbe significantly (-2mV/C), raising Ic considerably (~60mV/decade). (Which, come to think of it, the only reason it survived is because you had the foresight to add a resistor in the first place..?!) Q4/Q10 has no such luxury so it's no surprise they went.
Adding emitter resistors, and preferably cascode (Wilson current mirror) will reduce or solve that issue. Emitter resistors swamp Vbe, reducing the effect of tempco. Typically 0.1V or more at design/maximum current is effective. So, at least 10 ohms here. A cascode reduces the active (bottom, current-setting) transistor's Vce to about a Vbe, keeping it nice and cool, meanwhile the top transistor dissipates the bulk of the power.
But more to the point, no need to mirror, just put the zener high-side and use two Q1+R3's as it were. They won't saturate quite as low, but that can be solved by using a pair of diodes instead of the 5V zener. And for that matter, the "ON" LED sounds like something that should just be a resistor anyway -- put it in the diode bias path say, no need to waste extra mA's. :-+
Some saturation voltage can be spared by using a Sziklai output instead of Darlington, say. Or by using a common-emitter PNP (Sziklai or not) output, though this makes compensation more annoying (loop gain is much higher with two cascaded CE stages!).
Overcurrent works up to a point, but notice it won't save short-circuit conditions because LED2 has more drop than Q5-Q7. So it can't pull all the way down.
Regulation also isn't great with the double Vbe tempco of Q9-Q10; the usual solution is a diff pair, maybe a 6.2V zener (lower tempco), maybe extra level shifting / gain increasing stuff (like diff pair with mirror load, into volt-amp stage); at which point you might as well use an op-amp. Or you can combine them by using a TL431 or similar (which is better described as, not an "adjustable zener", but an open-collector op-amp with a conspicuously large yet suspiciously stable 2.50V (or other for variants) input offset voltage), for a quite stable output indeed (low Zo, low tempco).
Tim
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Overcurrent works up to a point, but notice it won't save short-circuit conditions because LED2 has more drop than Q5-Q7. So it can't pull all the way down.
Tim
1ohm + 1,3V = 3,3V for red LED good enough
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What's the idea behind C3?
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The drop from the LED was suspicous to me too. It is close, but should be OK with 2 x V_BE from the darlington stage and in addition Q8. So it's close with 3 transistors versus one LED. The LED should be red and more like an old style one with more like 1.5 V Vf and not a modern high efficiency one with higher Vf.
In the current circuit the foldback divider adds even more, at least at higher voltage, though not with a dead short. So maybe a high a forward voltage for the LED could explain some problem with the fold back.
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The drop from the LED was suspicous to me too. It is close, but should be OK with 2 x V_BE from the darlington stage and in addition Q8. So it's close with 3 transistors versus one LED. The LED should be red and more like an old style one with more like 1.5 V Vf and not a modern high efficiency one with higher Vf.
In the current circuit the foldback divider adds even more, at least at higher voltage, though not with a dead short. So maybe a high a forward voltage for the LED could explain some problem with the fold back.
The VBE of the series pass transistors will lower than normal if they are dissipating quite a bit of power, which will make it harder for Q8 to turn off the series pass transistors via the LED.
The VBE of the series pass transistors needs to be reviewed when operating at their maximum expected power dissipation, which may not necessarily be at maximum output current, and the operation of the over-current clamp circuit needs to be reviewed for correct operation under such conditions.
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Hi magic,
C3 give you a better dynamic responce.
Kind regards,
Bram
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Other than the need for emitter degeneration on the current mirror transistors, it looks good to me.
Vbe current limiter Q8 could be replaced with a differential pair to lower the sense voltage across the current shunt.
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Other than the need for emitter degeneration on the current mirror transistors, it looks good to me.
Vbe current limiter Q8 could be replaced with a differential pair to lower the sense voltage across the current shunt.
Hi David,
Would you be able to point me in the direction of an example? I dont quite follow how a differential pair could be implemented there.
Thanks
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Other than the need for emitter degeneration on the current mirror transistors, it looks good to me.
Vbe current limiter Q8 could be replaced with a differential pair to lower the sense voltage across the current shunt.
Hi David,
Would you be able to point me in the direction of an example? I dont quite follow how a differential pair could be implemented there.
Thanks
or current mirror
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To make a lower voltage (diff pair) current sense, you usually need something like this:
https://www.seventransistorlabs.com/Images/Discrete_Tube_Supply.png (https://www.seventransistorlabs.com/Images/Discrete_Tube_Supply.png)
Obviously this is part of a switching circuit, but the three transistor (PNP diff pair + NPN VAS) motif will get you there. Tail current will have to be from a small CCS; or maybe a resistor from the highest pass transistor base, hm.
Also nice to just reduce dissipation.
Tim
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Other than the need for emitter degeneration on the current mirror transistors, it looks good to me.
Vbe current limiter Q8 could be replaced with a differential pair to lower the sense voltage across the current shunt.
Hi David,
Would you be able to point me in the direction of an example? I dont quite follow how a differential pair could be implemented there.
Tektronix designed a lot similar discrete voltage regulators with differential pairs which were later replaced with operational amplifiers. They almost always included foldback current limiting. The linear regulators from the 7603 mainframe, shown below, are a good example.
In this design, the -50 volt supply is used as a reference for all of the other regulators so that they track when powering up. All NPN pass elements are used because power PNPs were unavailable or expensive, explaining the odd configuration for the negative regulators.
Looking at the +15 volt regulator, differential pair Q936 monitors current shunt resistor R935, comparing the current to a reference voltage provided by R936 and R939. R937 implements foldback current limiting. Like your design, the current limit is implemented by removing base drive from the first driver transistor, in this case through CR925.
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The Tek circuit requires a negative rail in order to work when the output is shorted to ground.
Tim's circuit doesn't need it, but it's a little... weird ;)
The left transistor in the PNP diff pair is at risk of saturating when it drives that NPN base, particularly if the NPN will be tasked with sinking a significant current away from the base of a power darlington and its Vbe becomes somewhat high. Tim deals with it by unbalancing the pair and shoving a few mA into the right transistor so that the emitters of the PNPs are hopefully higher than the base of the NPN. This surely adds offset voltage to the pair and likely some degree of thermal drift; in Tim's application it was of no concern because the circuit was in the feedback loop of the TL431.
I think the circuit below may be worth experimenting with. It's just three identical NPNs and powered solely by base-emitter voltage of the output darlington.
It's a fractional bandgap reference: the voltage at point e2 is (or tries to be) 1.05·Vbe(Q1)-Vbe(Q2) = 0.05·Vbe(Q1) + (Vbe(Q1)-Vbe(Q2)). The first term is about 30mV at room temp and decreasing 0.1mV/°C (obviously), the second term is about 20mV at room temp and increasing 0.07mV/°C, because resistors R3,R4 cause Q1,Q2 to run at about 2:1 current ratio (these currents must be high enough that R1,R2 current and Q3 base current are irrelevant and don't upset the ratio). The two errors almost cancel out, yielding approximately 50mV threshold and -0.03mV/°C drift. All transistors work at more than 0.5V Vce, a much safer margin against saturation.
If 50mV is too low, setting R1=470Ω and R3=150Ω changes it to 120mV.
All of those pair-based circuits (mine is sensitive to Q1 and Q2 matching) are susceptible to thermal difference between matched transistors. Usually 2mV threshold shift is expected per 1°C of difference.
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Oh yeah, I have this one floating around too:
(https://www.seventransistorlabs.com/Images/Low_Sat_CCS.png)
Same idea, but an actual linear application. Should've linked this first. :P
The left transistor in the PNP diff pair is at risk of saturating when it drives that NPN base, particularly if the NPN will be tasked with sinking a significant current away from the base of a power darlington and its Vbe becomes somewhat high. Tim deals with it by unbalancing the pair and shoving a few mA into the right transistor so that the emitters of the PNPs are hopefully higher than the base of the NPN. This surely adds offset voltage to the pair and likely some degree of thermal drift; in Tim's application it was of no concern because the circuit was in the feedback loop of the TL431.
Spot on. :-+ Notice the ~100mV offset at the diff input means there's about as much Vce to spare -- so it doesn't need to be unbalanced as such, but if one uses this for an adjustable current limit, it won't quite go all the way to zero, for this reason. In that case, imbalance is needed.
I think the circuit below may be worth experimenting with. It's just three identical NPNs and powered solely by base-emitter voltage of the output darlington.
It's a fractional bandgap reference: the voltage at point e2 is (or tries to be) 1.05·Vbe(Q1)-Vbe(Q2) = 0.05·Vbe(Q1) + (Vbe(Q1)-Vbe(Q2)). The first term is about 30mV at room temp and decreasing 0.1mV/°C (obviously), the second term is about 20mV at room temp and increasing 0.07mV/°C, because resistors R3,R4 cause Q1,Q2 to run at about 2:1 current ratio (these currents must be high enough that R1,R2 current and Q3 base current are irrelevant and don't upset the ratio). The two errors almost cancel out, yielding approximately 50mV threshold and -0.03mV/°C drift. All transistors work at more than 0.5V Vce, a much safer margin against saturation.
If 50mV is too low, setting R1=470Ω and R3=150Ω changes it to 120mV.
All of those pair-based circuits (mine is sensitive to Q1 and Q2 matching) are susceptible to thermal difference between matched transistors. Usually 2mV threshold shift is expected per 1°C of difference.
Nice one. Lower voltage, similar number of components; doesn't need external ref. Probably harder to adjust? Mmm, a bias current into the divider (b1) might still do it (without skewing the tempco too badly?).
Thermal matching definitely one of the drawbacks of these -- monolithic pairs are boutique and discretes track poorly, especially around heat, like in a power supply. On the upside, neither circuit needs much Vce so the self-heating error will be small.
Also, matched (but NOT monolithic!) pairs are available, which is nice for repeatable manufacture of circuits like this, as long as self-heating is managed.
Tim
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Probably harder to adjust? Mmm, a bias current into the divider (b1) might still do it (without skewing the tempco too badly?).
Maybe it would work without making things significantly worse, and they aren't great anyway. R3 and R4 voltages are only approximately equal, and Q3 base current is not very well defined. At least it simulates in the ballpark of where it ought to be, not sure IRL.
Major change of course requires changing both the Q1:Q2 current ratio and Q1 Vbe-multiplier gain.
The whole idea is stolen from LM10, but simplified significantly ;)
(For starters, LM10 really includes a second full blown opamp buffering its 200mV reference).
Things get easier when a reference voltage is available. Hard to tell which of those circuits is worse :P
The voltage reference must sink Q1 current and there is still some reliance on resistors and not perfectly defined Vbe's (like Q3) to set bias currents and differential pair balance. But it works down to zero (offset aside) and adds only two BOM items, so there is that.
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The 50mV voltage source V2 above could be replaced even with a resistor. Then Vbe of power transistors is used as the reference. Protection threshold will decrease when they get hot, which may or may not be acceptable or desirable.
As usual with those simple circuits, you pay for simplicity with weird quirks and experimentation to see if it works out OK.
Want a very accurate limit - use a a chip like LM10 :P