Magnetic coupling

[Junkers]

I'm currently developing a crank angle sensor circuit for a small 49cc 2 stroke motor. The role of the circuit is to detect the presence of the magnets on flywheel and interpret the analogue voltage, producing either a logic low or high for the sake of a FPGA. However the presence of noise from the magneto is coupling into my hall effect sensor and the wires which adjoin it to the conditioner/FPGA. The net effect of this is causing all sorts of erratic behaviour e.g. LCD producing random characters/FPGA being reset. Below is a schematic of the hall sensor/conditioner itself:



Currently the 3 wires between the hall effect sensor and the FPGA/Power source are unshielded, I will change this later today. What I'm having a hard time understanding is that even if only the ground wire between the sensor and the FPGA is connected, it's still acts as a viable path for noise to travel through. I would of expected ground to just "sink" whatever noise is present. Can anyone explain why this might be and how I might be able to get around it? How can I electrically isolate both power and ground so that no noise can reach the FPGA? I should mention that the power source is a 11.1V LiPo battery.

[Zero999]

When I first looked at that circuit, I thought the gain was too high but on closer inspection, it won't work: Q4's base is permanently connected to +V via R8.

According to the datasheet for th eTLE4905G, it has an open collector digital output so all those transistors are unnecessary.
http://www.datasheets.pl/hall_effect_sensors/TLE49X5G.pdf

[Junkers]

When I first looked at that circuit, I thought the gain was too high but on closer inspection, it won't work: Q4's base is permanently connected to +V via R8.

According to the datasheet for th eTLE4905G, it has an open collector digital output so all those transistors are unnecessary.
http://www.datasheets.pl/hall_effect_sensors/TLE49X5G.pdf

Well spotted, I misinterpreted what I have on veroboard. The final BJT sources its input from a common collector topology which the image should now reflect. The hall effect sensor is an A1302, not a TLE49X5G. I just provided the schematic for illustration, it wasn't meant to be for any real emphasis. I can confirm the circuit works. The noise is my main concern.

[mjkuwp]

Are you 100% sure the bad signals are caused by EMI?  A 2 stroke engine will not have very smooth rotation of the crank, the rotations come from explosions.  One hopes the flywheel stabilizes the rotation sufficiently but maybe not.  just food for thought.

Nominally, I think you only need a pull-up resistor to interface that chip with a micro.


If you want to try another IC, BU52040H is nice one.  It is a bipolar latch.  It goes to one logic state on the N pole and the other logic state with the S pole of the magnet with some hysteresis in between.  There are other sensors that work like this.  If you have alternating N and S poles it may be  better to use a bipolar sensor.

Another thing you might try is a current loop instead of a voltage signal.  Not that I have a lot of experience with this, but in general this is a technique used in factories to mitigate issues with noise. 

[dmills]

One immediate spot is that 5V to the pull up is IMHO suspicious for an FPGA,  most of which top out at 3.3V or so.
What does the input protection on the FPGA board look like (Please tell me this is not hooked straight to a pin on the gate array)?

The fact that it acts up with only the ground connected (presumably only at one end) leads me to think capacitive coupling from the HT lead rather then magnetic is a possibility if combined with poor ground layout on the FPGA board.
How is the ground handled on the FPGA? Plane or something long and thin?
What is the decoupling like?

Ferrite may help, as would an opto coupler right at the input to the logic board (You could then add maybe 22 ohms in series with both power and ground to help isolate things.

Regards, Dan.

[Junkers]

So it took a little longer to get around to tinkering with this than I had hoped but things have come along well.

@dmills
The ground is a hexagonal plane on the bottom layer. It's a dev board, a chinese knock off unfortunately. Decoupling isn't great as there is potential for noise to feed through both the signal and power lines. I had considered adding an opto isolater for the sake of the signal line but question its practical value if noise can still couple through the power line. I wasn't aware that a resistor alone could aid noise suppression. How does that work? Parasitic inductance?

I think what you mentioned about the overly high input signal may of really been the cause of my issues here. The actual voltage being fed into the FPGA was around 4.5V. The FPGA is an Altera Cyclone IV which has internal clamping diodes to protect from over voltage. I thought I may be able to get away with it, thinking the clamping diodes would bring the signal down to 3.3V. In reality I think the diodes weren't stabilizing as "cleanly" as I'd hoped hence they were sinking my input signal and disrupting the supply to the FPGA. This might also explain why the FPGA was producing junk characters on the LCD.  Here's what I'm referencing anyway:



@mjkuwp
I was initially. Considering what I mentioned above I'm still not sure how the ground along was introducing noise. There are obviously some other elements at play. I've replaced the original signal lines with some shielded cat 5 network cable and connected the shield to ground on the sensor side. Seems to be doing the job for now. Let's see how we go.