Hey all,
I've decided to splash out on an FPGA (finally!) as I'm really interested in learning to program in a parallel manner, along with the whole reconfigurable hardware stuff seems absolutely awesome! So I've got myself a Altera Cyclone IV development board, it features a couple of onboard devices like SRAM, 16bit R2R VGA DAC amongst a USB UART converter etc.
I've never actually used an FPGA, merely a CPLD so it took me a couple of attempts to learn how to use the PLL megafunctions etc. but most of the Altera tutorials were pretty useful. What I'm wondering however is:
After writing a simple VGA generation function, I want to match it to a ROM megafunction so I can display a simple image on my LCD. I've got the sync and timing working, I'm struggling however matching up my VGA section to the ROM section. I'm using the Altera block diagram method, along with writing all my parts in VHDL. The problem I'm coming across though is I'm trying to interface my VGA block with a ROM block. I've set my ROM address, clock and data pins as inputs/outputs (respectively) but quartus seems to think that I want to use these as dedicated digital pins, messing up my hopes of using any other peripherals. I've got a feeling I'm doing my VHDL wrong by declaring the I/O for the ROM in the entity port section but any form of help would be really beneficial!
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity VGATest1 is
port(
ClkIn: in std_logic;
R, B: out std_logic_vector(4 downto 0);
G: out std_logic_vector(5 downto 0);
HSO, VSO: out std_logic;
VRomAddr: out std_logic_vector(14 downto 0);
VRomDat: in std_logic_vector(7 downto 0);
VRomClk: out std_logic
);
end VGATest1;
The sections labelled VRomXXXX are what I want to internally connect to my ROM megafunction.
Cheers!