LLC secondary leakage inductance / Layout

[iliya31]

Hello, probably most of the people that have designed LLC converter had faced the problem I will describe.
When the LLC converter is designed with center tapped transformer and integrated inductance things come critical.
First of all both leakage inductance ( shorted secondary windings ) must be equal as possible. Otherwise large current disbalance will occur on secondary switches.
Another critical part is the parasitic secondary inductance that is coming from the layout. That parasitic inductance could create large current disbalance on secondary switches.
So the question is related with the layout. Drain track layout is perfectly matched on both transistors, but how do you match and should you, source track layout.

Here I have to mention first revision layout I didn't  have matched drain paths and one of the switches raised its temperature with 30 degrees more than the other ( current disbalance ), With the second revision I populated one PCB and it works fine, but than I populated one more and it seems there is disbalance cause one of the switches temperature is larger than the other.

[TimNJ]

Have you measured the leakage inductances of the transformers? Are they consistent between different samples? Have you tried to swapping the transformers? Put the transformer from the PCB which "works fine"  into the board which is not working as well. Does the behavior reverse?

It's good practice to match the distance of the PCB paths as much as possible, but I think the contribution of PCB trace mismatch is probably small in relation to the leakage inductances looking into the secondary windings. Depends on the transformer. If you measure 100's of nH looking into the secondary winding, then a few 10's of nH mismatch due to PCB is probably not a huge deal.

[iliya31]

I measured the leakage difference before solder it. difference was 3% ( 33uH and 34uH ). About the secondary leakage yes if it is only 10nH the reflected one will be n^2*Ln which is 2560nH and that adds huge difference.
So I am wondering if I have to to take considerations on the layout source - capacitor path.

[temperance]

Did you measure the current in both synchronous rectifiers?