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Offline promachTopic starter

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LNA circuit
« on: August 01, 2019, 04:15:08 pm »
I am trying to simulate a LNA circuit from the book "Design of CMOS RF Integrated Circuits and Systems"

However, it is still not working. Any help ?





mosfet_018.lib

Code: [Select]
* modified for use with LTSpice; DM 8/19/2008
*
* 0.18u CMOS process
*
* NMOS transistor model name: NM
* PMOS transistor model name: PM


*-----------------------------------------------------------------------
.subckt NM D G S B
+params: W=10u L=1u
M1 D G S B NM L={L} W={W} AS={1.1u*W} PS={2.2u+W} AD={1.1u*W} PD={2.2u+W}
.ends

* ----------------------------------------------------------------------
* NMOS transistor model
* ----------------------------------------------------------------------
.MODEL NM NMOS LEVEL=49
* ----------------------------------------------------------------------
************************* SIMULATION PARAMETERS ************************
* ----------------------------------------------------------------------
* format    : LTspice
* model     : MOS BSIM3v3
* ----------------------------------------------------------------------
*                        TYPICAL MEAN CONDITION
* ----------------------------------------------------------------------
+VERSION = 3.1            TNOM    = 27             TOX     = 4.1E-9
+XJ      = 1E-7           NCH     = 2.3549E17      VTH0    = 0.354505
+K1      = 0.5733393      K2      = 3.177172E-3    K3      = 27.3563303
+K3B     = -10            W0      = 2.341477E-5    NLX     = 1.906617E-7
+DVT0W   = 0              DVT1W   = 0              DVT2W   = 0
+DVT0    = 1.6751718      DVT1    = 0.4282625      DVT2    = 0.036004
+U0      = 327.3736992    UA      = -4.52726E-11   UB      = 4.46532E-19
+UC      = -4.74051E-11   VSAT    = 8.785346E4     A0      = 1.6897405
+AGS     = 0.2908676      B0      = -8.224961E-9   B1      = -1E-7
+KETA    = 0.021238       A1      = 8.00349E-4     A2      = 1
+RDSW    = 105            PRWG    = 0.5            PRWB    = -0.2
+WR      = 1              WINT    = 5e-9              LINT    = 2.351737E-8
+DWG     = 1.610448E-9
+DWB     = -5.108595E-9   VOFF    = -0.0652968     NFACTOR = 2.4901845
+CIT     = 0              CDSC    = 2.4E-4         CDSCD   = 0
+CDSCB   = 0              ETA0    = 0.0231564      ETAB    = -0.058499
+DSUB    = 0.9467118      PCLM    = 0.8512348      PDIBLC1 = 0.0929526
+PDIBLC2 = 0.01           PDIBLCB = -0.1           DROUT   = 0.5224026
+PSCBE1  = 7.979323E10    PSCBE2  = 1.522921E-9    PVAG    = 0.01
+DELTA   = 0.01           RSH     = 6.8            MOBMOD  = 1
+PRT     = 0              UTE     = -1.5           KT1     = -0.11
+KT1L    = 0              KT2     = 0.022          UA1     = 4.31E-9
+UB1     = -7.61E-18      UC1     = -5.6E-11       AT      = 3.3E4
+WL      = 0              WLN     = 1              WW      = 0
+WWN     = 1              WWL     = 0              LL      = 0
+LLN     = 1              LW      = 0              LWN     = 1
+LWL     = 0              CAPMOD  = 2              XPART   = 0.5
+CGDO    = 7.7E-10        CGSO    = 7.7E-10        CGBO    = 1E-12
+CJ      = 1.010083E-3    PB      = 0.7344298      MJ      = 0.3565066
+CJSW    = 2.441707E-10   PBSW    = 0.8005503      MJSW    = 0.1327842
+CJSWG   = 3.3E-10        PBSWG   = 0.8005503      MJSWG   = 0.1327842
+CF      = 0              PVTH0   = 1.307195E-3    PRDSW   = -5
+PK2     = -1.022757E-3   WKETA   = -4.466285E-4   LKETA   = -9.715157E-3
+PU0     = 12.2704847     PUA     = 4.421816E-11   PUB     = 0
+PVSAT   = 1.707461E3     PETA0   = 1E-4           PKETA   = 2.348777E-3     



*-----------------------------------------------------------------------
.subckt PM D G S B
+params: W=10u L=1u
M1 D G S B PM L={L} W={W} AS={1.1u*W} PS={2.2u+W} AD={1.1u*W} PD={2.2u+W}
.ends

* ----------------------------------------------------------------------
* PMOS transistor model
* ----------------------------------------------------------------------
.MODEL PM PMOS LEVEL=49
* ----------------------------------------------------------------------
************************* SIMULATION PARAMETERS ************************
* ----------------------------------------------------------------------
* format    : LTSPICE
* model     : MOS BSIM3v3
* ----------------------------------------------------------------------
*                        TYPICAL MEAN CONDITION
* ----------------------------------------------------------------------
+VERSION = 3.1            TNOM    = 27             TOX     = 4.1E-9
+XJ      = 1E-7           NCH     = 4.1589E17      VTH0    = -0.4120614
+K1      = 0.5590154      K2      = 0.0353896      K3      = 0
+K3B     = 7.3774572      W0      = 1E-6           NLX     = 1.103367E-7
+DVT0W   = 0              DVT1W   = 0              DVT2W   = 0
+DVT0    = 0.4301522      DVT1    = 0.2156888      DVT2    = 0.1
+U0      = 128.7704538    UA      = 1.908676E-9    UB      = 1.686179E-21
+UC      = -9.31329E-11   VSAT    = 1.658944E5     A0      = 1.6076505
+AGS     = 0.3740519      B0      = 1.711294E-6    B1      = 4.946873E-6
+KETA    = 0.0210951      A1      = 0.0244939      A2      = 1
+RDSW    = 127.0442882    PRWG    = 0.5            PRWB    = -0.5
+WR      = 1              WINT    = 5.928484E-10   LINT    = 3.468805E-8
+DWG     = -2.453074E-8
+DWB     = 6.408778E-9    VOFF    = -0.0974174     NFACTOR = 1.9740447
+CIT     = 0              CDSC    = 2.4E-4         CDSCD   = 0
+CDSCB   = 0              ETA0    = 0.1847491      ETAB    = -0.2531172
+DSUB    = 1.5            PCLM    = 4.8842961      PDIBLC1 = 0.0156227
+PDIBLC2 = 0.1            PDIBLCB = -1E-3          DROUT   = 0
+PSCBE1  = 1.733878E9     PSCBE2  = 5.002842E-10   PVAG    = 15
+DELTA   = 0.01           RSH     = 7.7            MOBMOD  = 1
+PRT     = 0              UTE     = -1.5           KT1     = -0.11
+KT1L    = 0              KT2     = 0.022          UA1     = 4.31E-9
+UB1     = -7.61E-18      UC1     = -5.6E-11       AT      = 3.3E4
+WL      = 0              WLN     = 1              WW      = 0
+WWN     = 1              WWL     = 0              LL      = 0
+LLN     = 1              LW      = 0              LWN     = 1
+LWL     = 0              CAPMOD  = 2              XPART   = 0.5
+CGDO    = 7.11E-10       CGSO    = 7.11E-10       CGBO    = 1E-12
+CJ      = 1.179334E-3    PB      = 0.8545261      MJ      = 0.4117753
+CJSW    = 2.215877E-10   PBSW    = 0.6162997      MJSW    = 0.2678074
+CJSWG   = 4.22E-10       PBSWG   = 0.6162997      MJSWG   = 0.2678074
+CF      = 0              PVTH0   = 2.283319E-3    PRDSW   = 5.6431992
+PK2     = 2.813503E-3    WKETA   = 2.438158E-3    LKETA   = -0.0116078
+PU0     = -2.2514581     PUA     = -7.62392E-11   PUB     = 4.502298E-24
+PVSAT   = -50            PETA0   = 1E-4           PKETA   = -1.047892E-4
* ----------------------------------------------------------------------



 

Offline duak

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Re: LNA circuit
« Reply #1 on: August 01, 2019, 05:29:47 pm »
I would start by changing the Vdd connection to Lbias to connect to a voltage source that does not saturate transistor M1.  The transistor data sheet should show a typical value.
 

Offline promachTopic starter

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Re: LNA circuit
« Reply #2 on: August 02, 2019, 01:25:17 am »
See the following LNA circuit with positive gain.

However, I am bit concerned with the values of Cin and C3.

Their values seem to affect the gain a lot

« Last Edit: August 02, 2019, 03:27:42 pm by promach »
 

Offline duak

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Re: LNA circuit
« Reply #3 on: August 02, 2019, 04:47:26 pm »
Do the MOSFETs have part numbers or are they devices that are part of some ASIC?  Is Vdd the recomended voltage and quiescent current for these devices?  Is this going to be used in a practical circuit?

As a starting point I would set DC bias to be about half of Vdd.  This should cause M1 and M2 to have the same drain to source voltage and allow both to run in the linear region.  If Vbias is too high, M1 will try to conduct too much current, saturate and not operate in its linear region.  You may have to adjust Vbias to find the highest gain.  If this doesn't work, try increasing Vdd and repeat.

I would also set Cd and C3 to zero as they affect AC gain.  You can restore them after the DC operating conditions are properly set.  I expect C3 set to 10p is way too high for 2.4 GHz.
 

Offline promachTopic starter

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Re: LNA circuit
« Reply #4 on: August 03, 2019, 02:46:38 am »
I have added series input impedance (Rs) and the shunt output load impedance (RL).

The LNA circuit still give negative gain.

Could anyone help ?


« Last Edit: August 03, 2019, 01:34:48 pm by promach »
 

Offline promachTopic starter

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Re: LNA circuit
« Reply #5 on: August 03, 2019, 04:14:04 pm »
I have modified the circuit to have a positive gain of 6.

But the gain is not enough.

Any help ?

 

Online SiliconWizard

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Re: LNA circuit
« Reply #6 on: August 03, 2019, 04:33:22 pm »
The transistors are quite big.

DO you know how to determine the values of the capacitors and inductors in this circuit, or are you just trying stuff?
 

Offline bson

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Re: LNA circuit
« Reply #7 on: August 03, 2019, 04:56:57 pm »
Well, the book says "2.4GHz" but you're feeding it 1GHz.  An LNA is low noise by trading off bandwidth and other factors.  So it looks like it works as intended perhaps?
 

Offline promachTopic starter

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Re: LNA circuit
« Reply #8 on: August 03, 2019, 05:17:43 pm »
@SiliconWizard

Those large transistor dimensions are needed for large gain

By the way, I do not know how to set the value for C3.

I am not sure how C3 affects the LNA circuit.

Any advice ?

For L1 and C1 parallel network, see the following book snippet.







« Last Edit: August 04, 2019, 12:52:08 am by promach »
 

Offline duak

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Re: LNA circuit
« Reply #9 on: August 04, 2019, 06:46:13 pm »
promach, did you try varying vbias to optimize gain?  Are you able to and have you tried increasing Vdd?  Do you know about resonant circuits? 

C3 is probably a parasitic capacitance put in the example for completness and should probably be minimized if possible.  It has the effect of reducing M1's gain at high frequencies and may be needed for stability.

This is a cascode gain stage that will have an inherently high output impedance.  If you need more gain into a 50 ohm load perhaps you can add a buffer stage composed of a source follower.
 

Offline promachTopic starter

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Re: LNA circuit
« Reply #10 on: August 05, 2019, 08:24:41 am »
What I do not understand is the strange AC response in the previous post just above with a sharp magnitude dip and abrupt 180 degrees phase shift at 2.9GHz


The transient response looks normal though.

 

Offline duak

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Re: LNA circuit
« Reply #11 on: August 06, 2019, 02:24:19 am »
What I do not understand is the strange AC response in the previous post just above with a sharp magnitude dip and abrupt 180 degrees phase shift at 2.9GHz


L1 & C1 form a parallel resonant circuit with a resonant frequency of 2.9 GHz.  At resonance, it will have a high impedance and attenuate the signal applied to M1's gate.  Below resonance, C1 is dominant and advances the phase, while above resonance L1 is dominant and retards the phase.
 
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Offline promachTopic starter

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Re: LNA circuit
« Reply #12 on: August 06, 2019, 02:40:01 am »
I have compiled everything into https://github.com/promach/LNA

Feel free to point out any issues with the circuit.
 

Online SiliconWizard

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Re: LNA circuit
« Reply #13 on: August 06, 2019, 03:27:31 pm »
Even Lbias/Cin will influence the overall frequency response, won't they?
 

Offline promachTopic starter

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Re: LNA circuit
« Reply #14 on: August 07, 2019, 01:18:01 am »
Anything wrong with Lbias = 3nH  and Cin = 1pF   ?
 

Offline promachTopic starter

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Re: LNA circuit
« Reply #15 on: August 16, 2019, 07:46:49 am »
Any comment on the .noise analysis simulation result below ?

 


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