Just a quick question about this...
In some cases, does it make sense to add some series resistance to the larger value capacitors to prevent parallel resonances between capacitors placed in parallel?
Yes, particularly bulk caps with large values and low ESR: ceramic and polymer especially. (Mind that, while ceramics aren't, polymers are available in many ESRs: shop accordingly. And tantalum are available in a higher but overlapping range; with ceramic and polymer being pervasive nowadays, tantalum aren't all that important anymore, and you don't have to worry about triggering thermite reactions, or buying conflict minerals.)
For example, use a 100 nF 0603 with 1-10 ohms in series, and a 1 nF 0402 in parallel with that combination, with the 1 nF placed closest to the bypassed pin? Then maybe with a ferrite bead and/or a series resistor of 1-10 ohms to suppress overall resonances?
If the 1nF 0402 has about 2nH ESL, and the 100n + 1R has about 6nH, that's Zo = (8nH/1nF) ~= 2.8 ohms, so 2.8 ohms ESR would be the best match.
The effect is this:
- If the supply impedance is generally high at these frequencies, then we can ignore it for purposes of the thought experiment;
- If you made the parallel combination without ESR, the peak impedance (at about 56MHz) can be many times higher than 2.8 ohms; likewise, the valley impedance nearby can be many times lower, but the peak is what we're most concerned about.
- With ESR, the impedance minima is raised to 2.8 ohms, but the maxima is also lowered to that.
For the stated 1 ohm, the damping will be modest, and the peak can be somewhat higher.
If this is sufficient for the application, great. If it needs lower impedance, you need a different network.
Note that going to 10n (0402) affords the same ESL towards the device but ~1/3 the resonant impedance and frequency, so ~1 ohm is suitable ESR.
Note the first condition: this is to illustrate this network in isolation. In a practical circuit, this network will be connected to a larger PDN with trace and via inductance, and then we must consider the response of that combination in turn. Probably, the highest frequency mode won't be hugely affected (it may rise in frequency, or drop somewhat in peak impedance, but probably not go away), but everything below that (i.e., resonances concerning the 100n) will be highly dependent.
Usually I try to get away with a single low inductance capacitor if the inductance is small enough, but at some point the wire bonding inductance is going to dominate and no matter what you do there's going to be a resonance.
Well, not necessarily a resonance, just a rising asymptotic impedance as seen by the chip inside. If the chip has onboard bypassing (there's always something, even if it's just all the gate capacitances acting together) maybe it can resonate. The chip also has some parallel resistance (digital logic consumes more current at higher voltages), and maybe series resistance too (spreading resistance).
There's not much you can do about that, and presumably -- since manufacturers generally recommend wiring chips this way, with adjacent bypass -- we can assume that the chip will be well-behaved in this case, whatever the underlying explanation.
Put another way, there isn't much we can do above 100MHz or so, on board -- the impedance is too low and even a tiny distance is too much stray inductance to deal with. Chips necessarily have to deal with that onboard.
Tim