| Electronics > Projects, Designs, and Technical Stuff |
| Logic IC power-off low side switch & decoupling |
| (1/1) |
| smoothVTer:
I've designed a clock subsystem that runs off a clipped sine wave oscillator. The oscillator itself has no enable pin; enable/disable is done by turning on/off the supply to the oscillator via an LDO. When the LDO is off, the oscillator is off, and the output of the oscillator is Hi-Z. This leads to the inverter oscillating about its resonant frequency due to Rf/Cf, a situation which burns power when the clock subsystem is supposed to be off. Thus I need to switch power to the inverter on or off. The easiest way to do this is for me to switch ground, as I can use a low side NFET to switch ground to the inverter using the same logic as the EN to the LDO. Question is: where dooes the decoupling cap go between when using a low side NFET is this fashion? Point #1 ( the GND pin of the inverter ) or #2 ( true ground point )? Does it matter? If it matters, why does it matter? For reference schematic: |
| ledtester:
Shooting from the hip here with an alternative idea... would a weak pull-down on the inverter input do the job? Another idea - use a NAND gate instead with the other input fed from EN. Or somehow pull the inverter input to GND when EN is low. |
| Ian.M:
If the inverter supply current is low enough, you can simply power it from the same I/O pin that drives the LDO EN signal. Reduce its decoupling to 1nF so you don't overload the pin for too long when switching it. , |
| smoothVTer:
Thanks, this solution works great! |
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