EEVblog® Electronics Community Forum
Electronics => Projects, Designs, and Technical Stuff => Topic started by: Noopy on January 25, 2021, 09:34:49 pm
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Let´s take a look into some logic ICs.
You can find an overview here: https://www.richis-lab.de/logic.htm (https://www.richis-lab.de/logic.htm)
(https://www.richis-lab.de/images/logic/01x02.jpg)
First logic IC is a CPLD, a Lattice ispLSI1016.
The LSI1016 is the smallest CPLD of this model range. The isp variant can be programmed in circuit.
16 logic blocks, 2000 gates, 96 register, 36 I/Os, max 80MHz, max delay 15ns
(https://www.richis-lab.de/images/logic/01x03.jpg)
The die is quite big: 6,1mm x 4,1mm
The datasheet states that the ispLSI1016 was manufactured with a 0,8µm process. Challanging my capabilities. :-/O ;D
(https://www.richis-lab.de/images/logic/01x04.jpg)
A 1992 design.
(https://www.richis-lab.de/images/logic/01x09.jpg)
A first revision?
Quite a lot of masks.
(https://www.richis-lab.de/images/logic/01x19.jpg)
(https://www.richis-lab.de/images/logic/01x20.jpg)
(https://www.richis-lab.de/images/logic/01x21.jpg)
In the dicing area there are quite some symbols and test structures.
(https://www.richis-lab.de/images/logic/01x06.jpg)
Developer initials? :-//
(https://www.richis-lab.de/images/logic/01x10.jpg)
Here you can see an I/O bondpad. On the top of the bondpad there is the input structure. At the left and the right sides of the bondpad there are the Push-Pull-transistors.
(https://www.richis-lab.de/images/logic/01x16.jpg)
Here you can see an input stage. I assume the big structures are clamping diodes. Behind the clamping diodes there is a small resistor and a transistor probably acting as a pull-up or pull-down.
(https://www.richis-lab.de/images/logic/01x18.jpg)
The structures are quite small but you can identify the big functional blocks.
(https://www.richis-lab.de/images/logic/01x31.jpg)
There are a lot of small structures between the bondpads which probably do some housekeeping.
Here you can see one of the more interesting circuits. Perhaps a small memory? Perhaps a multiplexer for connecting the distributed memory cells?
(https://www.richis-lab.de/images/logic/01x08.jpg)
Global logic block and I/O cell. Between the two you can spot the 16 lines of the output routing pool.
(Quite likely, you can´t be 100% sure.)
(https://www.richis-lab.de/images/logic/01x32.jpg)
Global logic block input logic array.
(https://www.richis-lab.de/images/logic/01x12.jpg)
Global routing pool, in there are quite a lot of interconnections with their memory cells.
More pictures here:
https://www.richis-lab.de/logic01.htm (https://www.richis-lab.de/logic01.htm)
:-/O
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SJDC - San Jose Design Center.
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Thank you, subscribed! :popcorn:
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A first revision?
Quite a lot of masks.
So, masks are used to amend errors on photo templates?
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No, by "masks" he meant the photo template. That's how they are called in the industry.
Each test structure represents one mask. And this is a lot indeed. But configurable devices are complex in their design.
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(https://www.richis-lab.de/images/logic/02x01.jpg)
D146, a BCD/7-segment decoder built by HFO.
(https://www.richis-lab.de/images/logic/02x03.jpg)
3,0mm x 1,8mm
(https://www.richis-lab.de/images/logic/02x04.jpg)
Test-transistor... :-/O
(https://www.richis-lab.de/images/logic/02x06.jpg)
The SN7446 datasheet contains a logical schematic (Texas Instruments, 1988).
(https://www.richis-lab.de/images/logic/02x07.jpg)
Well we find everything shown in the shematic.
The two input gates at the inputs A-D are marked in pink. The purple squares are the output transistors of the eight gates.
Between the inputs you see the lamptest circuit (green) and the blanking circuit (black).
The outputs of the input gates are connected to the decoder matrix (dark green) containing both, the connection matrix and the AND-gates. The big gate of the blanking circuit is placed in this area too. The blue parts are the pull-up-resistors for the decoder.
On top of the decode area there are seven NOR-gates with two or three inputs (orange). There are yellow pull-up-resistors and the last parts are the output transistors (red).
(https://www.richis-lab.de/images/logic/02x09.jpg)
Here you can see the input gates.
The first gates are built with an input stage (buffer or AND), a phase splitter and an output lowside transistor. There is no highside transistor but there is a diode connecting the pull-up-resistor of the phase splitter to the output. In the second gates they spared the phase splitter.
The input of the gates are built with transistors with big base areas in which there are one (buffer) or two (AND) emitter areas forming the inputs. The buried collector is the output of the gate input stage.
(https://www.richis-lab.de/images/logic/02x15.jpg)
In the middle of the die there is the decoder containing 19 multi emitter transistors.
(https://www.richis-lab.de/images/logic/02x13.jpg)
The upper contact is connected to the collector. The lower contact is connected to the base area. In the base area there are some emitters connected to the outputs of the input gates.
There is one rotated transistor. That´s the big gate for the blanking of the 0. This gate works with the same input signals so it was reasonable to place the gate in this area.
(https://www.richis-lab.de/images/logic/02x11.jpg)
You can spot every logical connection formed with a emitter and its contact.
But what´s that? There is an additional connection not shown in the SN7445 datasheet: B1/a2
(https://www.richis-lab.de/images/logic/02x10.jpg)
With this connection you get two more segments.
In my view that 6 looks better. ;D
(https://www.richis-lab.de/images/logic/02x08.jpg)
Here you see the seven NOR-gates and the output transistors.
(https://www.richis-lab.de/images/logic/02x05.jpg)
Nothing special...
There is an substrate connection at every transistor to prevent ground bouncing in the die.
https://www.richis-lab.de/logic02.htm (https://www.richis-lab.de/logic02.htm)
:-/O
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Minor corrections:
(https://www.richis-lab.de/images/logic/02x17.jpg)
Compared to the 7446 there are two additional connections (yellow).
(https://www.richis-lab.de/images/logic/02x16.jpg)
Symbol 6 and symbol 9 are different to the 7446. Symbol 12 is not different.
=> The D146 is more like a 74246 not like a 7446. :-+
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(https://www.richis-lab.de/images/logic/03x01.jpg)
Now let´s take a look into a ispLSI1024.
(https://www.richis-lab.de/images/logic/03x02.jpg)
The LSI1024 has one megablock more than the LSI1016.
(https://www.richis-lab.de/images/logic/03x03.jpg)
The die is 6,5mm x 5,8mm.
(https://www.richis-lab.de/images/logic/03x06.jpg)
(https://www.richis-lab.de/images/logic/03x07.jpg)
(https://www.richis-lab.de/images/logic/03x08.jpg)
(https://www.richis-lab.de/images/logic/03x09.jpg)
(https://www.richis-lab.de/images/logic/03x11.jpg)
A lot of test structures.
(https://www.richis-lab.de/images/logic/03x16.jpg)
There are also some more complex structures in the slicing area.
(https://www.richis-lab.de/images/logic/03x04.jpg)
The LSI1024 was designed in 1991 while the LSI1016 was designed in 1992 (perhaps the second revision?).
(https://www.richis-lab.de/images/logic/03x05.jpg)
HD24-00, the first revision of the "HD24"?
(https://www.richis-lab.de/images/logic/03x13.jpg)
Push/Pull-Transistors and input protection at the bondpads.
(https://www.richis-lab.de/images/logic/03x20.jpg)
...
A lot of small circuits are placed in the bondpad area.
(https://www.richis-lab.de/images/logic/03x15.jpg)
The LSI1024 is quite similar to the LSI1016 but here we have a third megablock. Since the third megablock is cut in two pieces they needed an additional connection line in the upper area.
(https://www.richis-lab.de/images/logic/03x23.jpg)
Let´s take a look into one of the eight segments of the megablock.
(https://www.richis-lab.de/images/logic/03x24.jpg)
Here there should be two I/O cells.
(https://www.richis-lab.de/images/logic/03x25.jpg)
Global-Logic-Block
(https://www.richis-lab.de/images/logic/03x26.jpg)
Global-Logic-Block connection array
(https://www.richis-lab.de/images/logic/03x27.jpg)
Global-Routing-Pool
Some more pictures:
https://www.richis-lab.de/logic03.htm (https://www.richis-lab.de/logic03.htm)
:-/O
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Love your threads, excellent stuff! Very interesting to look under the bonnet, so to speak.
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Thanks for the positive feedback! :-+ That keeps me taking more pictures. 8)
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I have some different controller periphery chips. Will post them here.
(https://www.richis-lab.de/images/chipset/01x01.jpg)
Mitsubishi M5L8288, a bus controller for a 8086 processor.
(https://www.richis-lab.de/images/chipset/01x02.jpg)
Two bondwires for the supply. The seven command outputs can sink more than 220mA. That is not too much for one bondwire but the voltage drop can cause switching problems.
(https://www.richis-lab.de/images/chipset/01x03.jpg)
Mitsubishi used two metal layers.
(https://www.richis-lab.de/images/chipset/01x06.jpg)
The name of the design?
(https://www.richis-lab.de/images/chipset/01x07.jpg)
Some symbols to check the production quality.
(https://www.richis-lab.de/images/chipset/01x08.jpg)
Around the die the two metal layers distribute the supply voltage.
(https://www.richis-lab.de/images/chipset/01x09.jpg)
The command outputs. Between the bondpads there are the big lowside transistors. On the left side of the bondpads there are the smaller highside transistors.
Wide metal stripes supply the outputs.
(https://www.richis-lab.de/images/chipset/01x10.jpg)
Here we have one of the weaker outputs. The lowside transistor (right of the bondpad) is bigger than the highside transistor (above the bondpad) but both are smaller than the transistors of the command outputs.
https://www.richis-lab.de/chipset01.htm (https://www.richis-lab.de/chipset01.htm)
:-/O
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(https://www.richis-lab.de/images/logic/04x01.jpg)
ispLSI1048E, the biggest CPLD of the LSI10xx family. The index E is a an update of the index C which is an update of the ispLSI1048.
(https://www.richis-lab.de/images/logic/04x03.jpg)
Although the ispLSI1048E is much more complex than the ispLSI1024 (https://www.richis-lab.de/logic03.htm (https://www.richis-lab.de/logic03.htm)) the die is smaller: 5,9mm x 4,7mm. It´s clearly a newer design.
(https://www.richis-lab.de/images/logic/04x04.jpg)
Yes, designed seven years after the ispLSI1024.
The lines are clearly thinner.
(https://www.richis-lab.de/images/logic/04x05.jpg)
There are circuits between the bonpads as we have seen in the smaller CPLDs.
(https://www.richis-lab.de/images/logic/04x11.jpg)
The LSI1048 consists of six megablocks each built with eight GLBs (global logic blocks). The 48 GLBs are placed in groups of four on the left and on the right side of the die.
The GRP (global routing pool) is integrated in the middle of the die.
(https://www.richis-lab.de/images/logic/04x06.jpg)
Here you see a group of four GLBs with it´s portion of the GRP.
(https://www.richis-lab.de/images/logic/04x07.jpg)
GLB
(https://www.richis-lab.de/images/logic/04x08.jpg)
GLB logic array
(https://www.richis-lab.de/images/logic/04x09.jpg)
GRP
(https://www.richis-lab.de/images/logic/04x12.jpg)
I don´t know why the GRP is not symmetrical. Well we don´t know how it is partitioned.
https://www.richis-lab.de/logic04.htm (https://www.richis-lab.de/logic04.htm)
:-/O
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These pictures are ... to "die" for!
:-DD
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...
D146, a BCD/7-segment decoder built by HFO.
...
(https://www.richis-lab.de/images/logic/05x01.jpg)
The D147 does the same as the D146 but the maximum output voltage is only 15V (vs. 30V of the D146).
(https://www.richis-lab.de/images/logic/05x02.jpg)
As we would have expected the design of the die is the same. Probably they did some binning.
(https://www.richis-lab.de/images/logic/05x03.jpg)
There is a small defect in the metal layer above one of the output transistors.
(https://www.richis-lab.de/images/logic/05x04.jpg)
And a nice pictures of the test-transistor. :-/O
https://www.richis-lab.de/logic02.htm (https://www.richis-lab.de/logic02.htm)
:-/O
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(https://www.richis-lab.de/images/logic/06x01.jpg)
For today I have a less interesting part: К555NE7 / K555IE7, the soviet version of the SN74LS193.
(https://www.richis-lab.de/images/logic/06x02.jpg)
Here we have the brown mold compound that allows light to get to the chip. In some circuits that leads to a strange behaviour as soon as you change the light incidence.
(https://www.richis-lab.de/images/logic/06x04.jpg)
Sorry, not the best pictures in my "career" (2,2mm x 2,2mm).
(https://www.richis-lab.de/images/logic/06x06.jpg)
The left test structure seems to be a normal NPN transistor. The right test structure could be a PNP transistor. :-//
(https://www.richis-lab.de/images/logic/06x07.jpg)
Here we have three different resistors. Probably base and emitter doping and a pinch-resistor.
https://www.richis-lab.de/logic05.htm (https://www.richis-lab.de/logic05.htm)
:-/O
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(https://www.richis-lab.de/images/logic/07x01.jpg)
IDT7472, a J/K-Master-Slave-Flip-Flop built by RIZ (Radioindustrie Zagreb).
(https://www.richis-lab.de/images/logic/07x03.jpg)
The die is secured in the package with the "glue" that holds the package together.
(https://www.richis-lab.de/images/logic/07x04.jpg)
(https://www.richis-lab.de/images/logic/07x05.jpg)
The die is 1,2mm x 1,2mm. The circuit is quite symmetrical.
(https://www.richis-lab.de/images/logic/07x09.jpg)
(https://www.richis-lab.de/images/logic/07x06.jpg)
The upper edge is damaged probably due to the sawing of the wafer.
There are seven mask revisions. The quality of the characters is quite bad.
(https://www.richis-lab.de/images/logic/07x08.jpg)
Here you see one of the two AND gates with six inputs. The emitter areas are the inputs. The base is connected to the supply and the collector is the output.
(https://www.richis-lab.de/images/logic/07x10.jpg)
At the lower edge there are the two output stages with a highside and a lowside transistor on both sides.
https://www.richis-lab.de/logic06.htm (https://www.richis-lab.de/logic06.htm)
:-/O
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(https://www.richis-lab.de/images/logic/08x01.jpg)
The V4001D built by the Funkwerk Erfurt in March 1983 is a CD4001B clone: four 2-input NOR
(https://www.richis-lab.de/images/logic/08x03.jpg)
The die is 1,5mm x 1,4mm.
(https://www.richis-lab.de/images/logic/08x06.jpg)
(https://www.richis-lab.de/images/logic/08x07.jpg)
etch marker and/or alignment control
(https://www.richis-lab.de/images/logic/08x05.jpg)
seven masks some modified two times
(https://www.richis-lab.de/images/logic/08x08.jpg)
The TI CD4001B datasheet contains a schematic. It is built with two NOT, one NAND and one more NOT.
There is also a schematic of the input protection circuit.
(https://www.richis-lab.de/images/logic/08x04.jpg)
The four NOR are easy to spot.
(https://www.richis-lab.de/images/logic/08x09.jpg)
(https://www.richis-lab.de/images/logic/08x10.jpg)
There are the two input protections (white) followed by the first push-pull-stage (NOT, purple).
The parallel connected highside transistors (yellow) and the serial connected lowside transistors (green) gives us the NAND. Interesting how dense the transistors are integrated.
The output highside transistor (red) is bigger than the output lowside transistor (blue) because the p-MOSFET is less powerful than the n-MOSFET.
Interesting point: At the output there is another protection circuit. A diode to Vdd and a small resistor that is a diode to Vss.
(https://www.richis-lab.de/images/logic/08x11.jpg)
Input protection: Here you can see the Rin acting as a Diode to Udd.
(https://www.richis-lab.de/images/logic/09x01.jpg)
(https://www.richis-lab.de/images/logic/09x02.jpg)
March 1986, same design.
https://www.richis-lab.de/logic07.htm (https://www.richis-lab.de/logic07.htm)
:-/O
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(https://www.richis-lab.de/images/logic/10x01.jpg)
One more V4001D built by the Uhrenwerk Ruhla in 1989.
(https://www.richis-lab.de/images/logic/10x02.jpg)
Same design but a little different auxiliary structures.
https://www.richis-lab.de/logic08.htm (https://www.richis-lab.de/logic08.htm)
:-/O
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(https://www.richis-lab.de/images/logic/11x01.jpg)
DL020D, a Dual-4-Input-NAND built by the Halbleiterwerk Frankfurt Oder. It´s a 74LS20.
We already had the D220 (https://www.richis-lab.de/wafer01.htm (https://www.richis-lab.de/wafer01.htm)) which is a 7420.
U1 => built in January 1986.
(https://www.richis-lab.de/images/logic/11x02.jpg)
The die is 1,1mm x 1,0mm. The symmetrical design is easy to see and there are a lot of unused parts. I´m sure the design was used for different logic gates by just changing the metal layer.
(https://www.richis-lab.de/images/logic/11x03.gif)
(https://www.richis-lab.de/images/logic/11x04.jpg)
(https://www.richis-lab.de/images/logic/11x05.jpg)
(https://www.richis-lab.de/images/logic/11x06.jpg)
With the background knowledge how a 74LS logic is usually built, we can reconstruct the circuit of the DL020 fairly easily. The diodes D1-D4 isolate the inputs against each other. Since the diodes are in the signal path Schottky diodes are used, which offer fast switching times. The diodes D5-D8 seem to be normal diodes. They protect the DL020 against negative voltages.
If there is no low level at any input resistor, R1 pulls the base of Q5 high. Q5 is a Schottky transistor. A Schottky diode between base and collector ensures that the transistor doesn´t saturate so switch-off is faster. Despite the Schottky diode there is a resistor between base and emitter too. Through this resistor free charge carriers can flow out of the active area.
Around Q5 the potentials are tapped which control the highside and the lowside transistor in the output stage. The highside transistor is a Darlington (Q7/Q8). Q7 is a Schottky transistor which guarantees a fast turn-off. In the place of Q8 a normal transistor is sufficient. Base-emitter resistors are added too (R6/R7). The resistor R8 is necessary, because during switching the lowside and the highside transistor become conductive at the same time for a very short time. During this period the current should be limited.
Q9 is the lowside transistor. Again, this is a Schottky transistor. The network R3/R4/Q6 can be found in a lot of 74LS-logic of other manufacturers. I´m not 100% sure why you need this circuit. I assume the Vbe of Q6 ensures a faster turn-on of Q9. Other suggestions?
(https://www.richis-lab.de/images/logic/11x07.jpg)
The pictures quality could be better but we can identify some parts and structures.
Here you can see two of the input structures, unused on the left side, used on the right side. The input signal is fed from the bottom edge. The horizontal line is connected to GND. The contacts at the upper edge are connected together.
One might expect that this is a transistor but there is no base area visible where two of the three contacts would have to be located. Instead the upper and lower contacts seem to be connected to the n-doped surface. The lower contact is slimmer than the upper one. With the background knowledge that there are usually Schottky diodes at the inputs of a 74LS-logic, these structures are quite argumentative. The lower contact is probably located on a heavily n-doped area which ensures an ohmic contact to the n-doping. Due to the high doping a small contact area is sufficient. The outlines which are barely visible are probably the vias in the insulating silicon oxide. The edges of the heavily n-doped area cannot be seen at the contact. A deeper, strongly n-doped layer conducts charges to the uppermost contact, where the metal layer rests directly on the "normal", weaker n-doped layer. Thus a Schottky diode is formed at the interface. The larger contact area is probably necessary due to the lower conductivity of the weaker n-doped material.
The contact in the middle of the structure is interesting. In most 74LS schematics, there are two Schottky diodes at each input. Here the protection diode seems to be a conventional diode. This can be assumed because another outline can be seen around the outline of the via. A strong n-doping would not serve any useful purpose at this point, it would even act as a low ohmic pull-down resistor. A p-doping on the other hand creates a conventional diode. The conventional diode is slower than a Schottky diode but it probably has advantageous properties in its function as a protection diode. Perhaps it can conduct higher currents in this process.
(https://www.richis-lab.de/images/logic/11x08.jpg)
The Schottky transistors can be recognized too. Usually, the structure of a Schottky transistor hardly differs from the structure of a normal transistor. It is sufficient to enlarge the base contact area so it contacts the collector area too. At the contact between the base metal and the collector area the desired Schottky diode is formed. These double contact can be seen even in the smaller transistors of the DL020D. The base contacts are quite large and have an edge where the base and collector regions meet under the metal layer (blue arrows).
In the case of the large lowside transistor in the bottom left corner of the image, a relatively large square can be seen in the area of the base contact. The square is an opening in the base area through which the metal layer can contact the collector area.
https://www.richis-lab.de/logic09.htm (https://www.richis-lab.de/logic09.htm)
:-/O
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(https://www.richis-lab.de/images/logic/12x01.jpg)
(https://www.richis-lab.de/images/logic/12x02.jpg)
Fairchild 9300, a 4Bit shift register.
(https://www.richis-lab.de/images/logic/12x03.jpg)
(https://www.richis-lab.de/images/logic/12x04.jpg)
The die is 2,1mm x 1,6mm.
There are two supply frames surrounding the die. At the lower edges you can see five a little bigger output transistors.
(https://www.richis-lab.de/images/logic/12x05.jpg)
8300? :-//
Z 6A is probably a mask revision.
In the lower left corner there are some more letters under the metal layer. It looks like 8300 and Z 3A.
https://www.richis-lab.de/logic10.htm (https://www.richis-lab.de/logic10.htm)
:-/O
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(https://www.richis-lab.de/images/logic/12x06.jpg)
I didn´t honor the 9300 enough!
The 9300 is one of the 9000 TTL logic Fairchild had invented. With the 9300 familiy Fairchild had an advantage over Texas Instruments. With the MSI (medium scale integration) of the 9300 familiy Fairchild was able to integrate more complex functions in one chip.
Later Texas Instruments outperformed Fairchild and today everybody knows the 74-family...
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(https://www.richis-lab.de/images/logic/13x01.jpg)
К155ЛA3 (K155LA3) a soviet SN7400: 4x 2-Input NAND
They used the brown mold compound you often see with soviet ICs. It´s a little darker than the mold compound of the KR597SA1 (https://www.richis-lab.de/Opamp25.htm (https://www.richis-lab.de/Opamp25.htm)). They sometimes had problems with light entering the package and influencing the integrated circuit.
(https://www.richis-lab.de/images/logic/13x02.jpg)
(https://www.richis-lab.de/images/logic/13x05.jpg)
The edge length is 1mm.
(https://www.richis-lab.de/images/logic/13x03.jpg)
(https://www.richis-lab.de/images/logic/13x06.jpg)
There are some squares to check the alignment of the masks.
And there are three characters. Probably ЛA3? :-//
(https://www.richis-lab.de/images/logic/13x04.jpg)
(https://www.richis-lab.de/images/logic/13x08.jpg)
At the input transistor there are some options but a lot less than in the DL020 (https://www.richis-lab.de/logic09.htm (https://www.richis-lab.de/logic09.htm)).
https://www.richis-lab.de/logic11.htm (https://www.richis-lab.de/logic11.htm)
:-/O
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Just a small Update to the К155ЛA3 (K155LA3) :
(https://www.richis-lab.de/images/logic/13x09.jpg)
There is a datasheet showing the schematic of the K115 chips.
(https://www.richis-lab.de/images/logic/13x02.jpg)
I have added "names" to the bondpads.
https://www.richis-lab.de/logic11.htm (https://www.richis-lab.de/logic11.htm)
:-/O
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(https://www.richis-lab.de/images/logic/14x01.jpg)
D172, a J/K-Master-Slave-Flip-Flop built by the Halbleiterwerk Frankfurt Oder. It´s similar to the SN7472.
LN stands for a production in September 1973 or in November 1979. We will see that it has to be 1979.
(https://www.richis-lab.de/images/logic/14x02.jpg)
(https://www.richis-lab.de/images/logic/14x03.gif)
Datasheet shows what is inside the D172. Picture quality is... Yes... ;D
(https://www.richis-lab.de/images/logic/14x07.jpg)
In the "Radio Fernsehen Elektronik" issue 16 / 1977 there is an article about the D172. The text tells us that the D172 was improved. The parts of the circuit were rearranged so it consumes less area. In addition the circuit itself was optimized.
The schematic shown in the RFE shows two differences to the datasheet. In addition to the protection diodes at all I/Os (red), a small auxiliary circuit was integrated (blue), which additionally interlocks the right and left halves of the circuit against each other.
(https://www.richis-lab.de/images/logic/14x09.jpg)
The Texas Instruments datasheet for the SN7472 shows the additional circuit as two AND gates.
(https://www.richis-lab.de/images/logic/14x03.jpg)
(https://www.richis-lab.de/images/logic/14x04.jpg)
The die in the D172 above has an edge length of 1.3mm. In the upper area the name D172 is shown in the metal layer.
A large part of the die is discolored. The component was defective. It is therefore likely that the discoloration was caused by this defect. However, the cause of the defect cannot be narrowed down.
(https://www.richis-lab.de/images/logic/14x05.jpg)
(https://www.richis-lab.de/images/logic/14x06.jpg)
The RFE article contains a black-and-white picture of the updated D172 and there is even a color picture on the front page.
In the lower right corner you can find the symbol of an AND gate, the logo of the "Zentrum für Mikroelektronik Dresden". The RFE article is appropriately written by an employee of the Zentrum für Mikroelektronik Dresden.
(https://www.richis-lab.de/images/logic/14x08.jpg)
Comparing the structures you can see that the design is the same. In the chip shown here just the logo is missing.
Since the RFE article from 1977 describes the design as new, it can be assumed that the chip was produced in 1979 not in 1973.
https://www.richis-lab.de/logic12.htm (https://www.richis-lab.de/logic12.htm)
:-/O
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Are you drunk or something?
Capacitors are extremely costly in ICs and are used in highly specialized cases where there is no other option. Why and where would you even want to see capacitors here?
And you can't see the point of making FPGAs, you just have no clue what is going on. Do you think ASICs happen out of thin air? They are designed and prototyped in FPGAs. Also ASICs are expensive and hard to impossible to update. But again, what it has to do with this thread?
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Are you drunk or something?
Something.
Capacitors are extremely costly in ICs and are used in highly specialized cases where there is no other option. Why and where would you even want to see capacitors here?
If u just need to twist a pair of wires together to make a cap, its not very expensive at all.
And you can't see the point of making FPGAs, you just have no clue what is going on. Do you think ASICs happen out of thin air? They are designed and prototyped in FPGAs. Also ASICs are expensive and hard to impossible to update. But again, what it has to do with this thread?
Its to do with the thread, because we have some programmable logic devices here have we not noticed?
There's nothing to prototype in a logic design that a computer cant just run virtually in an ordinary gate model. (Like Logisim.), the actual hardware plumbing itself needen't really be tested at all if the electrical engineer actually wires it up properly like he was supposed to learn how to. its just a gate circuit conversion to real electricity, I dont think an fpga even helps with that anyway, and its actually the only job to do.
FPGA's are just for people that cannot do hardware and want to pretend they are electrical engineers when they are not.
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Ah, you are one of the old people that can't cope with the new technology and think everyone needs to be stuck in the 70s simply because you can't learn new things anymore.
You really have no clue what you are talking about when it comes to FPGAs.
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Ah you grabbed my king off the board cause then u get to win. :-DD
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Nah, he writes from a parallel universe in which capacitors are gain devices.
Posts about capacitor amplifiers every few weeks and now also capacitor logic :D
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How is not knowing how to do something supposed to make someone look cool.
Oh I know, its when you all dont know the same thing together!!!!
You cool guys know something I don't, but when that happens to me it doesn't work for some reason, cause everyone seems to know the thing I dont.
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why do they call them dies, is it because the indians' come out of their genocide pit to get ya if you get this far in engineerin'?
Racism is not tolerated here, first and only warning.
FPGA's are just for people that cannot do hardware and want to pretend they are electrical engineers when they are not.
Settle down mate, post on topic or don't post at all.
Your rant about what you feel people can & can't do and what you think of them is out of place here.
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I deleted his first post, one more and he's banned, I'm not wasting time cleaning his mess up.
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(https://www.richis-lab.de/images/logic/15x01.jpg)
(https://www.richis-lab.de/images/logic/15x02.jpg)
DL003, a brother of the 74LS03 built in the Halbleiterwerk Frankfurt Oder. The DL003 contains four NAND gates with two inputs. S3 tells us it was produced in March 1984.
(https://www.richis-lab.de/images/logic/15x03.jpg)
It turns out that the die is very similar to the DL020 (https://www.richis-lab.de/logic09.htm (https://www.richis-lab.de/logic09.htm)) which offers two NAND gates with four inputs each. The two devices are based on the same design. The metal layer creates the functions of various logic circuits with the underlying elements. Fittingly the designation DL003 is found on the upper edge.
(https://www.richis-lab.de/images/logic/15x05.jpg)
The direct comparison with the DL020 shows three small differences apart from the metal layer. The red and the yellow resistors are not directly connected to Ucc in the DL020, so that they can be used more variably. The green marked resistor is also not directly connected to Ucc on the DL020. It offers an additional tap too.
(https://www.richis-lab.de/images/logic/15x04.jpg)
(https://www.richis-lab.de/images/logic/15x06.jpg)
(https://www.richis-lab.de/images/logic/15x07.jpg)
The circuit of the DL003 is a bit simpler compared to the DL020 because the highside transistor at the output is missing. In addition the DL003 lacks the resistor that bridges the base-emitter of Q5 in the DL020 and ensures a faster switch-off.
(https://www.richis-lab.de/images/logic/16x01.jpg)
The DL003 seen here was manufactured in June 1986 (U6).
(https://www.richis-lab.de/images/logic/16x02.jpg)
It can be seen that this module is already based on the new design which was the basis for the DL020 (produced in January 1986). On the right edge, the number 04 has been incremented to 05. Most likely this is the revision of the metal layer, which had to be adjusted.
The use of a common basic design that creates different gate arrangements via the metal layer makes the production more efficient because you need less masks (at least back in the days in GDR).
https://www.richis-lab.de/logic13.htm (https://www.richis-lab.de/logic13.htm)
:-/O
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(https://www.richis-lab.de/images/logic/17x01.jpg)
Some more standard logic. The Texas Instruments SN7400 contains four NAND gates with two inputs each. The Soviet variant of this gate is the K155LA3 (https://www.richis-lab.de/logic11.htm (https://www.richis-lab.de/logic11.htm)).
(https://www.richis-lab.de/images/logic/17x03.jpg)
The edge length of the die is 0,93mm.
You can find the Ti logo in the lower right corner. In addition to the contacts to the substrate, the frame structure also shows some auxiliary structures that allow monitoring the manufacturing quality.
In contrast to the K155LA3, no retentions for alternative functions can be seen here.
(https://www.richis-lab.de/images/logic/17x04.jpg)
946C :-//
Name and revision?
(https://www.richis-lab.de/images/logic/17x02.jpg)
The datasheet shows the generally known circuit of a NAND gate.
Push-pull output stages are located at the outputs. The SN7403 also offers four NAND gates with two inputs each, but has just open-collector outputs. For the output high-side transistor, a single transistor was powerful enough. The D220 (https://www.richis-lab.de/wafer01.htm (https://www.richis-lab.de/wafer01.htm)) uses a Darlington pair for the highside.
(https://www.richis-lab.de/images/logic/17x05.jpg)
(https://www.richis-lab.de/images/logic/17x06.jpg)
The individual elements of the gates can be easily identified. :-+
https://www.richis-lab.de/logic14.htm (https://www.richis-lab.de/logic14.htm)
:-/O
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(https://www.richis-lab.de/images/logic/18x01.jpg)
Now here we have a SN7402. It contains four NOR gates.
(https://www.richis-lab.de/images/logic/18x02.jpg)
The edge length of the die is 0,93mm. The Ti logo is located in the lower right corner. There is a certain similarity to the SN7400, but at the same time independent of the circuit itself there are some differences in the structures.
While on the SN7400 the ground potential is distributed via a frame structure, on the SN7402 there are GND traces that run through the circuit.
The number sequence 946C, which is shown on the SN7400, cannot be assigned. The numbers 02C on the SN7402 on the other hand certainly refer to the specific designation of the logic module.
The protection diodes at the inputs are clearly visible in the SN7400 but not in the SN7402.
(https://www.richis-lab.de/images/logic/18x03.jpg)
The circuit diagram in the datasheet shows how the gates work. The two input transistors control two parallel connected driver transistors, which drive a push-pull stage.
(https://www.richis-lab.de/images/logic/18x04.jpg)
(https://www.richis-lab.de/images/logic/18x05.jpg)
The components of the circuit diagram can all be found on the die. Only the protection diodes are not directly visible. The bondpads, which represent the inputs, have additional frame structures that are not found on the outputs. This suggests that the protection diodes were integrated under the bondpads.
https://www.richis-lab.de/logic15.htm (https://www.richis-lab.de/logic15.htm)
:-/O
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(https://www.richis-lab.de/images/logic/19x01.jpg)
One more standard logic part. The Texas Instruments SN7404 contains six inverter gates.
(https://www.richis-lab.de/images/logic/19x02.jpg)
The die is 1,1mm x 0,8mm in size. The basic design is the same as in the 7402 (https://www.richis-lab.de/logic15.htm (https://www.richis-lab.de/logic15.htm)). The 04C characters in the center of the die refer to the specific variant of the 74 family.
(https://www.richis-lab.de/images/logic/19x03.jpg)
The datasheet shows the unsurprising structure of an inverter. The input transistor is followed by a driver stage which generates differential control signals to drive both highside and lowside transistor.
(https://www.richis-lab.de/images/logic/19x04.jpg)
A inverter gate is less complex than a NOR gate in the 7402 but since there are six inverters the 7404 requires significantly more area. Three inverters are located in the lower half of the die and the other three inverters are located in the upper half of the die.
(https://www.richis-lab.de/images/logic/19x05.jpg)
(https://www.richis-lab.de/images/logic/19x06.jpg)
The individual circuit parts can be easily identified.
https://www.richis-lab.de/logic16.htm (https://www.richis-lab.de/logic16.htm)
:-/O
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(https://www.richis-lab.de/images/logic/20x01.jpg)
The SN7474 contains two Flip-Flops.
(https://www.richis-lab.de/images/logic/20x02.jpg)
The die is 1,4mm x 1,0mm.
The design is the same as in the SN7402 (https://www.richis-lab.de/logic15.htm (https://www.richis-lab.de/logic15.htm)) and in the SN7404 (https://www.richis-lab.de/logic16.htm (https://www.richis-lab.de/logic16.htm)). However a GND metal frame is integrated like in the SN7400 (https://www.richis-lab.de/logic14.htm (https://www.richis-lab.de/logic14.htm)). The characters 74C in the metal layer match the model designation.
https://www.richis-lab.de/logic17.htm (https://www.richis-lab.de/logic17.htm)
:-/O
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(https://www.richis-lab.de/images/logic/21x01.jpg)
SN7493, a binary counter.
(https://www.richis-lab.de/images/logic/21x02.jpg)
In the datasheet you can find the logical block diagrams of the 7490, the 7492 and the 7493, counting to 10, to 12 and to 16.
(https://www.richis-lab.de/images/logic/21x03.jpg)
The dimensions of the die are 1.4mm x 1.3mm.
With the large protection diodes the design is similar to the SN7400 (https://www.richis-lab.de/logic14.htm (https://www.richis-lab.de/logic14.htm)).
(https://www.richis-lab.de/images/logic/21x04.jpg)
In the lower right corner the numbers 93 and some not connected elements can be found, including the basis for two additional bondpads. These structures and the fact that the SN7490, the SN7492 and the SN7493 share a datasheet suggest that the three devices are based on the same design and just the metal layer has to be changed.
https://www.richis-lab.de/logic18.htm (https://www.richis-lab.de/logic18.htm)
:-/O
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(https://www.richis-lab.de/images/logic/22x01.jpg)
One more 9000 logic (like the 9300: https://www.richis-lab.de/logic10.htm (https://www.richis-lab.de/logic10.htm)).
The 9334 is a 8Bit latch.
(https://www.richis-lab.de/images/logic/22x03.jpg)
The datasheet shows a functional diagram of the 9334.
In the lower area the eight memory cells can be seen. In the upper area differential signals are generated from the potentials addressing the individual memory cells. Enable and Data are linked.
(https://www.richis-lab.de/images/logic/22x02.jpg)
The die is 2,1mm x 1,5mm.
(https://www.richis-lab.de/images/logic/22x05.jpg)
In the upper area the metal layer depicts the characters AO and 34. Under the metal layer on the left edge you can barely see the characters AO34U. 34 probably marks the variant 9334 within the 9300 logic family.
(https://www.richis-lab.de/images/logic/22x06.jpg)
At the bottom of the die there are the characters U6B, which may represent a revision designation.
(https://www.richis-lab.de/images/logic/22x07.jpg)
The eight memory cells are easy to recognize. The eight lines in the middle of the dies are also striking. These are the differential address lines, the data signal and the enable signal. The clear signal is routed between the memory cells and the middle signal distribution in kind of a ring line.
(https://www.richis-lab.de/images/logic/22x04.jpg)
The vertical stripes represent the 16 AND gates. They are NPN transistors with multiple emitters. The red stripe is the base area. A pull-up resistor connects it to the positive supply. A smaller, isolated, red area represents the collector contact. The collector is the output of the gate. The horizontally running leads contact square emitter areas within the base region. If one of the lines carries a low potential, it sinks the positive base potential and a low level is set at the output. Only if a high level is present at all connected lines the respective gate can output a high level at the collector.
https://www.richis-lab.de/logic19.htm (https://www.richis-lab.de/logic19.htm)
:-/O
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(https://www.richis-lab.de/images/logic/23x01.jpg)
The DS8205 produced in the Halbleiterwerk Frankfurt Oder is a so-called 1 out of 8 binary decoder. One of eight outputs can be activated via three inputs. The DS8205 corresponds functionally to the Intel P8205 and the 74S138.
The string T8 stands for a manufacturing in August 1985.
(https://www.richis-lab.de/images/logic/23x02.jpg)
The datasheet of the DS8205 shows the simple design. The input signals are processed to differential control signals. At each output a quad NAND gate is connected to the necessary control lines.
(https://www.richis-lab.de/images/logic/23x03.jpg)
The die of the DS8205 is 1,9mm x 1,2mm. The auxiliary structures known for the HFO can be found on it. At the top right corner there are the numbers 03, which indicate the revision of the design. The numbers below appear to have a reference to the masks used. At the bottom edge in the milling line the remains of the crosses can be seen that allow to check the alignment of the masks against each other. At the top left the designation 8205 is shown.
At the top right are the input bondpads. The output bondpads are equipped with large push-pull transistors. The long NAND gates are integrated in the right area. The vertical transistors contacting a horizontal line represent an input of the respective NAND gate.
(https://www.richis-lab.de/images/logic/24x01.jpg)
This DS8205 was manufactured in November 1985 (TN).
(https://www.richis-lab.de/images/logic/24x02.jpg)
At the top right you can see that the revision has been incremented to 04. However, there are no visible differences to revision 03. A DS8205 manufactured in February 1998 also contains a revision 04.
(https://www.richis-lab.de/images/logic/25x01.jpg)
The DS8205 shown here was manufactured in September 1989 (X9). It contains the revision 05 as well as a DS8205 with the date code X3 (March 1989).
(https://www.richis-lab.de/images/logic/25x02.jpg)
Revision 05 also shows no functional differences to revisions 03 and 04. However, the contact areas from the metal layer to the silicon appear to be slightly larger.
Perhaps the old masks had reached the end of their service life or the process has changed slightly and new masks were therefore created.
(https://www.richis-lab.de/images/logic/25x03.jpg)
(https://www.richis-lab.de/images/logic/25x04.jpg)
In detail you can see the Schottky transistors described in more detail with the DL020 (https://www.richis-lab.de/logic09.htm (https://www.richis-lab.de/logic09.htm)). The base contact is wider than the base area and thus simultaneously contacts the collector area (green). A Schottky diode is formed at the interface between the metal and the collector doping. The more powerful transistors have an additional contact to the collector surface (red) in addition to the contact to the base surface.
https://www.richis-lab.de/logic20.htm (https://www.richis-lab.de/logic20.htm)
:-/O
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(https://www.richis-lab.de/images/logic/26x01.jpg)
The Motorola MC14094B is a 8Bit shift register with tri-state outputs. The datasheet advertises the device as pin compatible with the CD4094B.
(https://www.richis-lab.de/images/logic/26x02.jpg)
The blockdiagram shown in the datasheet shows the structure of the MC1409B. There are eight registers connected in series, which represent a shift register. Next to each register a latch is integrated which controls a tri-state output stage. At the end of the shift register the data is output via Q s and Qs.
(https://www.richis-lab.de/images/logic/26x07.jpg)
(https://www.richis-lab.de/images/logic/26x03.jpg)
The die is 2,00mm x 1,85mm in size. The structures under the metal layer are poorly visible.
(https://www.richis-lab.de/images/logic/26x04.jpg)
(https://www.richis-lab.de/images/logic/26x05.jpg)
With the characters 14094B the designation of the circuit is shown on the die. To the left of this are some markers that allow to check the alignment of the masks against each other. The meaning of the characters C60E remains unclear.
(https://www.richis-lab.de/images/logic/26x06.jpg)
The individual sections of the MC14094B are clearly visible. Between the output bondpads are the push-pull output stages (red). The largest part of the area is taken up by the two times four areas that contain registers, latches and drivers for the output stages (purple). In the upper right area a conspicuously large driver is integrated (green), which amplifies the clock signal sufficiently to be able to supply the many transistors in the rest of the circuit.
(https://www.richis-lab.de/images/logic/26x08.jpg)
(https://www.richis-lab.de/images/logic/26x09.jpg)
The details of the circuit are difficult to see due to the poor contrast of the different areas.
https://www.richis-lab.de/logic21.htm (https://www.richis-lab.de/logic21.htm)
:-/O
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(https://www.richis-lab.de/images/logic/27x01.jpg)
(https://www.richis-lab.de/images/logic/27x02.jpg)
The RCA CA3161 is a BCD/7-segment decoder similar to the D146 / D147 (https://www.richis-lab.de/logic02.htm (https://www.richis-lab.de/logic02.htm)), but it also contains constant current sinks. 7-segment displays can thus be connected directly without series resistors. The module provides a current flow between 18mA and 35mA.
(https://www.richis-lab.de/images/logic/27x13.jpg)
The datasheet shows the character containing a minus sign and the letters E, H, L and P in addition to the numbers.
(https://www.richis-lab.de/images/logic/27x03.jpg)
The edge length of the die is about 2mm.
(https://www.richis-lab.de/images/logic/27x04.jpg)
10397B could be the internal designation of the circuit.
(https://www.richis-lab.de/images/logic/27x05.jpg)
The individual circuit blocks can be identified relatively easily. At the lower edge there is the input buffer (yellow). With the help of the bias generator in the left area, the input signals are evaluated. Towards the top the buffer outputs the input signals differentially.
The binary value is first converted into a decimal value (green) before another circuit (blue) generates the necessary 7-segment control signals.
The seven output stages are integrated in the upper area of the die (red).
(https://www.richis-lab.de/images/logic/27x06.jpg)
The input buffers are designed like differential amplifiers and provide differential outputs. At the upper end the current value is output via lowside transistors.
(https://www.richis-lab.de/images/logic/27x09.jpg)
(https://www.richis-lab.de/images/logic/27x07.jpg)
The differential binary value, here 1110, controls a matrix containing eight long transistors. Judging by the structure and the wiring they are probably NPN transistors. The binary value is applied to the base areas. Subsequently all but one of the 15 continuing lines are switched to high via the emitter areas. The inactive line stands for the selected symbol.
(https://www.richis-lab.de/images/logic/27x08.jpg)
This is followed by another matrix that controls the final stages of the device. Seven lines run horizontally, which stand for the seven segments. On the left they are connected to current sources, which provide a high level in the inactive state. The output stages that receive a high level are activated and the corresponding segments light up. Consequently the matrix must deactivate the segments that are not needed. On the right side five lines are led to the output stages a, b, c and d. The lines for segments f and g run to the left of the matrix. The area of these lines gives the impression of having a special function. In fact, however, it is just an undercrossing of the metal layer.
The exact function of the areas below the matrix remains unclear. From above another supply is fed from the V+ potential, but it is distributed differently from the previous matrix. Since the inactive control line must deactivate segments and the matrix should remain inactive with the high levels of the other control lines, it must almost be a PNP structure. The substrate could be used as ground. However, there seems to be a lack of a strong low level to drive the selected transistor strip. One can only assume that the leakage currents are high enough to drive the transistor and thus pull the necessary lines to a low level. :-//
(https://www.richis-lab.de/images/logic/27x11.jpg)
The datasheet shows the implementation of the current limitation. There is a resistor in the emitter path of the output transistor. As the current increases the voltage drop across the resistor increases and the lower transistor diverts more and more base current from the output transistor. Eventually the specified LED current is established.
(https://www.richis-lab.de/images/logic/27x10.jpg)
The large output transistors are integrated directly at the bondpads. A slightly thicker GND line guarantees the necessary current carrying capacity. Around the GND line there is the current limiter.
Darlington transistors control the output stages. There are quite large resistors in their collector paths.
(https://www.richis-lab.de/images/logic/27x12.jpg)
On the die of the CA3161 considerable areas are reserved for another function. Two very large output stages are integrated in the lower left corner. Above the power amplifiers there is an input buffer as it is also used for the 7-segment control. It was obviously intended to switch on the two output stages alternately.
If you follow the lines you can see that the bondpad for the control of these output stages would be located at the right edge. The bondpad for segment e placed there would then be moved to the upper right corner. Similarly in the lower left corner, the bondpad for input 2^1 could be moved to the right freeing up two bondpads for the two outputs in that area.
Perhaps the additional circuit would allow multiplexing of two 7-segment displays.
https://www.richis-lab.de/logic22.htm (https://www.richis-lab.de/logic22.htm)
:-/O
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I wasn´t happy with my explanation how these two matrices in the CA3161 do they job.
Now I know what the problem was! That is a I2L, a integrated injection logic!
(https://www.richis-lab.de/images/logic/27x14.jpg)
The binary value, here 1110, is located with its complementary value at the lower edge of the matrix. A low level at an input pin leads to an active low level at the lower edge of the matrix (2^3). A high level leaves the respective input open (2^0 - 2^2). The complementary connections behave correspondingly inverse to this.
The matrix contains a so-called Integrated Injection Logic, I2L. If there is a low level at one of the vertical stripes, the outputs remain inactive. Without a low level, the Integrated Injection Logic switches a low level to the outputs.
A total of 15 lines lead to the left. 15 lines are sufficient because no active control is needed for the number 8. The selected line remains inactive. All other lines carry a low potential.
(https://www.richis-lab.de/images/logic/27x17.jpg)
At the input of an Integration Injection Logic there is the injector, a PNP transistor whose base is connected to the ground potential and thus serves as a current source. In this circuit, the injector is not directly connected to the positive supply, but to a current source. This probably reduces the power dissipation. Any number of lowside transistors can be connected to the input as a signal source. The outputs of an I2L gate are then again NPN transistors which switch to GND. Again, theoretically any number of outputs are possible.
On the die of the CA3161 the NPN transistors of an I2L gate can be seen as long vertical base strips, in which square emitter areas are located. An injector strip is integrated between two of these strips. The injector does not necessarily have to be designed as a long strip parallel to the NPN transistors. A single block at the upper end would be sufficient in principle. However, the long strip reduces the switching delay between the top and bottom NPN transistors. This feature can be critical, especially with long I2L gates, such as those present here.
The PNP transistor, operating as an injector, forms between the middle and adjacent p-doped strips. The n-doping, in which the strips are embedded, represents the base, which is connected to the ground potential via a buried heavy n-doping.
(https://www.richis-lab.de/images/logic/27x19.jpg)
At first glance the structure of the NPN transistors corresponds to the usual design. In an n-doped well with a low-lying, heavily n-doped feed line, there is a p-doped area containing heavily n-doped elements. Normally, the lower n-doping represents the collector and the upper n-doping forms the emitter of the NPN transistor. However, here the transistor structure is used inverted. The lower well is operated like an emitter and the individual squares in the base doping operate as collectors. Therefore, the above schematic describes the physical structure more accurate.
The common transistor structure is advantageous because a thin base layer can be set there. Most of the electrons, which are released from the emitter, fly through the base zone and reach the collector. The doping gradient that occurs in the base region also has a beneficial effect on this movement. In an inversely operated transistor, the electrons that then leave the large-area collector have many more opportunities to leave through the base. Only a few electrons reach the small emitter.
NPN transistors certainly allow inverted operation. The breakdown voltage and and gain are then usually much lower. The same applies to the cutoff frequency. On the other hand the lower saturation voltage is advantageous. The negative effects can be advantageously influenced to a certain extent by the shape and doping of the structures. A more detailed consideration can be found, for example, in the IEEE article "Device Physics of Integrated Injection Logic" (IEEE Transactions on Electron Devices Volume 222, Issue 3, March 1975).
(https://www.richis-lab.de/images/logic/27x18.jpg)
If no signal is present at the input of the I2L strip, the current flow through the injection transistor (pink) ensures that the NPN transistors become conductive and pull the outputs to ground potential (green).
If there is a low level at the input of the I2L strip, the free charge carriers of the injection transistor are diverted from the base area of the NPN transistor so that it remains blocked.
(https://www.richis-lab.de/images/logic/27x16.jpg)
Integrated Injection Logic can be integrated into an n-doped substrate. However in the CA3161 there are also ordinary transistors, which usually require a p-doped substrate.
The paper "Integrated Injection Logic-Present and Future," published in the IEEE Journal of Solid-State Circuits (Volume 9, Issue 5, October 1974), shows how seven masks can be used to integrate I2L areas alongside conventional transistors. As usual for normal transistors a heavily p-doped substrate is used to isolate the individual transistors from each other. Above this is the NPN transistor with a buried, highly doped collector feed line. Heavily p-doped confinement structures provide lateral isolation.
The I2L region is isolated by a heavily n-doped well. The collector feed line can be used as the bottom element. In addition just some strongly n-doped, deep-reaching lateral boundary structures are required. This also explains the different appearance of the boundery structures of normal transistors and I2L regions on the die of the CA3161.
(https://www.richis-lab.de/images/logic/27x15.jpg)
This first I2L matrix is followed by another I2L matrix, which ultimately controls the final stages of the device. Seven lines run horizontally, which stand for the seven segments. They are connected to current sources on the left, which provide a high level in the inactive state. The output stages that receive a high level are activated and the corresponding segments light up. Consequently, the matrix must deactivate the segments that are not needed. For this reason the number 8 is not present here, because without active intervention all segments are active and accordingly an 8 is displayed. Five lines lead to the right to the output stages a, b, c and d. The lines for the segments f and g run to the left of the matrix.
As with the first matrix, this is a Integrated Injection Logic too. At the top left is a dual power source. One path supplies the injector of the lower matrix, the second path supplies the injector of the matrix you can see here. Since the lines are not too high, it was sufficient to design the injector as a single element above the transistor strips.
Where no low level is present (X), the I2L transistors become active and deactivate the segments connected there (here d, e, f and g).
https://www.richis-lab.de/logic22.htm (https://www.richis-lab.de/logic22.htm)
:-/O
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Texas Instruments SN7400 Quad NAND gate in flat pack package. 1965. :)
(https://upload.wikimedia.org/wikipedia/commons/5/53/SN7400_1965.jpg)
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This last photo is absolutely MIGHTY. Amazingly cool.
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Imagine all those chips produced - how many tons of gold you may get from the SN74 series? ::)
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(https://www.richis-lab.de/images/logic/28x01.jpg)
The DL074 built by the Halbleiterwerk Frankfurt Oder contains two edge-triggered D-Flip-Flops. The datasheet specifies a maximum clock frequency of 25MHz. With the designation PL074, the component seen here is a so-called "Bastlertyp" (hobbyist type) that does not necessarily comply with all specifications. The signs U9 stand for a production in September 1986.
(https://www.richis-lab.de/images/logic/28x02.jpg)
(https://www.richis-lab.de/images/logic/28x03.jpg)
There is a large and relatively thick carrier in the package, which improves the heat dissipation of the circuit.
(https://www.richis-lab.de/images/logic/28x05.jpg)
(https://www.richis-lab.de/images/logic/28x04.jpg)
The dimensions of the dies are 3,0mm x 1,8mm.
(https://www.richis-lab.de/images/logic/28x06.jpg)
The designation on the side of the die shows that this is actually a DL193. The DL193 is a binary counter with four digits, it consequently contains four flip-flops. Apparently, an alternative metal layer has been developed that connects two of the flip-flops completely and independently to the outside. Synergies were often sought in the GDR semiconductor industry, as it became increasingly difficult over time to produce the many different integrated circuits due to limited capacities.
(https://www.richis-lab.de/images/logic/28x07.jpg)
The revisions of eight masks can be seen on the side. The metal layer was revised once. Perhaps revision 2 is the variant that turns the DL193 into the DL074.
(https://www.richis-lab.de/images/logic/28x08.jpg)
In the middle of the die, some unused vias can be seen. These probably resulted from the adaptation to the functionality of the DL074.
https://www.richis-lab.de/logic23.htm (https://www.richis-lab.de/logic23.htm)
:-/O
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Hm, it seems I was wrong:
The DL074 has 14 pins. This PL074 has 16 pins. >:D
I assume this part got a wrong label and it is just a D193, nothing more.
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(https://www.richis-lab.de/images/logic/29x01.jpg)
(https://www.richis-lab.de/images/logic/29x02.jpg)
No let´s take a look into a real DL074. The DL074 from the Halbleiterwerk Frankfurt Oder is a dual flip-flop with set and reset inputs. As a low power Schottky TTL the DL074 corresponds to the 74LS74.
V2 stand for a production in February 1987.
(https://www.richis-lab.de/images/logic/29x03.jpg)
(https://www.richis-lab.de/images/logic/29x04.jpg)
The die was damaged during exposure, but most of the structures can be seen. The edge length of the die is 1,2mm. The numbers 03 on the top edge show that this is a third revision. Several masks are shown on the lower edge and in the left area.
(https://www.richis-lab.de/images/logic/31x01.jpg)
The DL074 seen here was manufactured in May 1988 (W5). It contains the same design as in the first DL074.
(https://www.richis-lab.de/images/logic/30x01.jpg)
With the characters W8 this DL074 was manufactured in August 1988.
(https://www.richis-lab.de/images/logic/30x02.jpg)
(https://www.richis-lab.de/images/logic/30x03.jpg)
The die of this DL074 is heavily damaged. Either the IC was electrically overloaded or there are signs of corrosion.
The numbers 05 on the right edge show that the design has been revised in the meantime. In the circuit itself, no differences to revision 04 can be seen. Just the unused edge area was made thinner and the bondpads were moved a little.
(https://www.richis-lab.de/images/logic/30x04.jpg)
(https://www.richis-lab.de/images/logic/30x05.jpg)
Due to the severe damage, the circuit parts are difficult to recognize.
https://www.richis-lab.de/logic24.htm (https://www.richis-lab.de/logic24.htm)
:-/O
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There are some updates to the DL logic, the AND and NAND gates to be exact.
The HFO used a basic design that is the same for the following three logic gates. The difference is just the metal layer.
(https://www.richis-lab.de/images/logic/15x01.jpg)
(https://www.richis-lab.de/images/logic/15x03.jpg)
We already had the DL003, a four 2-Input NAND gates.
(https://www.richis-lab.de/images/logic/15x04.jpg)
(https://www.richis-lab.de/images/logic/15x06.jpg)
(https://www.richis-lab.de/images/logic/15x07.jpg)
(https://www.richis-lab.de/images/logic/15x08.jpg)
The schematic in the Radio Fernsehen Elektronik states there should be a Push-Pull output stage but here it is missing although the circuit parts are on the die. :-//
(https://www.richis-lab.de/images/logic/16x01.jpg)
(https://www.richis-lab.de/images/logic/16x02.jpg)
A second DL003 lacks the highside stage too.
(https://www.richis-lab.de/images/logic/32x01.jpg)
The DL008 is new. It contains four 2-Input AND gates.
(https://www.richis-lab.de/images/logic/32x03.jpg)
(https://www.richis-lab.de/images/logic/32x07.jpg)
(https://www.richis-lab.de/images/logic/32x06.jpg)
(https://www.richis-lab.de/images/logic/32x05.jpg)
The AND is pretty similar to the NAND and hey, here we have the highside stage too!
(https://www.richis-lab.de/images/logic/32x04.jpg)
Here you can see the different metal layers while the basic design is the same.
(https://www.richis-lab.de/images/logic/33x01.jpg)
(https://www.richis-lab.de/images/logic/33x02.jpg)
A second DL008, now this one is a little different!
(https://www.richis-lab.de/images/logic/33x03.jpg)
If you put the revisions 4 and 5 of the DL008 next to each other, you can easily see the differences. The revision refers to the metal layer and applies specifically to the respective logic device. The DL020 with revision 03 (right) already used the newer design, which is also used by the DL008 with revision 05. If you ignore the metal layer, you can see the evolution of the basic design.
The active elements of the basic design did not change between the revisions, only the resistors were adapted. The top resistor (cyan) has been changed from a transparent material, presumably the base doping to a narrow strip, of the standard resistor material. It is the 75Ω resistor in the supply line of the output stage. It is present on each of the symmetrically constructed sides once in the upper and once in the lower area.
The other two resistors in the upper section (red/yellow) were permanently connected to the Ucc potential in the earlier revision. In the newer revision 04 they have been relocated so that they can be used more freely. In the DL008 the used resistor (red) is still connected to Ucc. But the Ucc line has been widened at this point. With the DL020, this resistor could be used as base-emitter resistor for the transistor VT1 (We will see that soon.) This would not have been possible with the older design.
In the lower section, next to the series resistor in the supply of the output stage, two resistors were also adapted, which in the older design were permanently connected to the Ucc potential (green). In the newer design, these are two resistors connected in series, whose center tap can be connected to the Ucc potential (center). With a different design of the metal layer, however, the two resistors can also be used independently of the Ucc potential (right).
(https://www.richis-lab.de/images/logic/11x01.jpg)
(https://www.richis-lab.de/images/logic/11x02.jpg)
Here we see the DL020 we already had. It contains two 4-Input NAND gates.
(https://www.richis-lab.de/images/logic/11x04.jpg)
(https://www.richis-lab.de/images/logic/11x05.jpg)
(https://www.richis-lab.de/images/logic/11x06.jpg)
And here we have the additional Base-Emitter-resistor that isn´t shown in the schematic in the Radio Fernsehen Elektronik. It seems like they tried to speed up Q5 (VT1) a little.
Update DL003 (4*2-IN-NAND):
https://www.richis-lab.de/logic13.htm
DL008 (4*2-IN-AND):
https://www.richis-lab.de/logic25.htm
Update DL020 (2*4-IN-NAND):
https://www.richis-lab.de/logic09.htm
:-/O
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A minor mistake:
The DL003 is the variant with open collector output so it´s normal the highside transistor is missing. ;D
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(https://www.richis-lab.de/images/logic/34x01.jpg)
(https://www.richis-lab.de/images/logic/34x02.jpg)
The V40098 from the Funkwerk Erfurt contains six inverting drivers, which are combined in a group of four and a group of two. Both groups can be switched off individually. The characters V9 show that the module was manufactured in September 1987. With a supply voltage of 5V, the signal delay time is a maximum of 160ns.
(https://www.richis-lab.de/images/logic/34x03.jpg)
The dimensions of the die are 2,2mm x 2,3mm.
(https://www.richis-lab.de/images/logic/34x05.jpg)
The die is labelled U40098. The components with the letter V on the housing are specified for operation in the extended temperature range from -25°C to 85°C. The components with the letter U are only specified for operation between 0°C and 70°C. Binning was probably done after packaging.
(https://www.richis-lab.de/images/logic/34x06.jpg)
The revisions of six masks can be seen in the bottom left-hand corner. The V4001 from the Funkwerk Erfurt (https://www.richis-lab.de/logic07.htm (https://www.richis-lab.de/logic07.htm)) and the V4001 from the Uhrenwerk Ruhla ("https://www.richis-lab.de/logic08.htm") show the revisions of seven masks.
(https://www.richis-lab.de/images/logic/34x04.jpg)
The individual functional blocks are easy to identify. Protective structures are integrated in the outer area (pink/purple). The six identical structures of the six drivers are located in the centre of the die (green/blue and yellow/red). A smaller circuit is integrated on the left for activating the group of two (orange). A Bigger circuit activates the group of four (cyan).
(https://www.richis-lab.de/images/logic/34x09.jpg)
The V40098 has the same protective structures at the inputs as the V4001 (https://www.richis-lab.de/logic07.htm (https://www.richis-lab.de/logic07.htm)). The V4001 contains a more detailed analysis of these structures.
(https://www.richis-lab.de/images/logic/34x08.jpg)
In contrast to the V4001, protective structures have also been integrated between Vdd and Vss. These are definitely two diodes.
(https://www.richis-lab.de/images/logic/34x07.jpg)
On closer inspection, the large push-pull transistors at the output can be clearly recognised. The activation signal is connected to the control circuit and is routed from driver to driver.
https://www.richis-lab.de/logic26.htm (https://www.richis-lab.de/logic26.htm)
:-/O
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(https://www.richis-lab.de/images/logic/35x01.jpg)
The U1525FC007 is a standard cell ASIC that was used in the Robotron A5105 educational computer. In this part of the documentation, only the structure and properties of the underlying standard cell design system U1520 are considered. A more detailed analysis of the functions of the U1525FC007 is provided in the third part of the documentation. The characters X8 stand for production in August 1989.
(https://www.richis-lab.de/images/logic/35x02.jpg)
The U1525FC007 is based on the U1520 standard cell system. This was a development in the Zentrum für Mikroelektronik Dresden, which later became part of the Carl Zeiss Jena combine. In addition to the U1520 standard cell system, the U1500 standard cell system and the U5200 gate arrays were available. A lot of information on all three systems can be found in the document "Applikative Informationen 4/88" published by VEB Applikationszentrum Elektronik Berlin.
Each of the three architectures has advantages and disadvantages. Simple gate arrays such as the U5200 system contain a fixed arrangement of simple gates and flip-flops. More complex logic blocks are build with combinations of the available gates. To implement the desired functions, only the wiring levels are structured in an application-specific way. This means that the so-called masters can be produced with the same mask set and only a few application-specific masks remain. In the case of the U5200, there are 3 masks.
If you build a circuit with standard cell ASICs such as the U1500 or the U1520, you can use a relatively large number of different standard cells. These gates and flip-flops have a specific, optimized structure. As a result, they require less area and usually have better dynamic behavior. In addition, you can select exactly the number of elements you need and arrange them very freely. However, this also makes the development of such ASICs more complex. Production is also more complex because all masks are application-specific. In the case of the U1500, there are 9 masks. In the case of the U1525, there are 12 masks. What all architectures have in common is that the majority of the structures are known and tested. This simplifies the implementation of an application-specific circuit.
The U1500/U1520 system offers over 40 different standard cells and enables the integration of up to 13.000 transistors. In 1988, a price range of 30-300 Ostmarks was quoted. "Economically favorable quantities" would therefore be 1.000 - 100.000 per year. For the U5200 gate array system, on the other hand, there is an "economic upper limit" of 10.000 units per year.
The standard cell ASICs U1500 and U1520 are based on the CSGT2 process. CSGT stands for "Complementary Silicon Gate Technology". It is a 5V CMOS process with a minimum structure size of 4µm. The operating clock of the process is typically 4MHz, the gate delay is specified as 5ns. Two different variants of the CSGT2 process were used for the U1500 and the U1520. The U1500 is based on the CSGT2/N process, the U1520 on the CSGT2/S process. Although the dynamic parameters of the two processes are different, it is said that neither process can be described as better in this respect. The CSGT2/S just allows higher packing densities because the standard cells are smaller. However, the manufacturing process is more complex.
The successor generations to U1500 and U5200 were the U1600 and U5300 systems, whose minimum structure width is just 1,5µm and which have two metal layers. With even larger chip areas, the maximum possible number of transistors increases to up to 100.000. The operating frequency increases to 25MHz, the gate delay decreases to a maximum of 1,6ns. RAM, ROM and PLA areas were then also available in the U1600 system.
(https://www.richis-lab.de/images/logic/35x18.jpg)
A little earlier, in the document "Applikative Information 3/88", there is a comparison of the advantages and disadvantages of the various product families. ...yeah, german language... ;)
(https://www.richis-lab.de/images/logic/35x19.jpg)
The picture above shows the rational areas of application in a somewhat simpler way. Standard cell ASICs were considered particularly useful for medium quantities. The range of applications expands towards more complex circuits.
(https://www.richis-lab.de/images/logic/35x03.jpg)
The "Fachbereichstandard" TGL 43876 describes how the standard cell ASICs U1500/U1520 were labeled. Unfortunately, however, the assignment of the description to the characters is slightly off. The designation U1525FC007 is explained as follows: U15 stands for this generation of standard cell ASICs. The 2 shows that the component was manufactured using the CSGT2/S process. The number 5 stands for the maximum chip size with an edge length of 7,5mm. F indicates that it is a ceramic package. The letter C indicates the usual operating temperature range. Finally, 007 is the specific type designation of the ASIC design.
(https://www.richis-lab.de/images/logic/35x04.jpg)
Table 2 of the "Fachbereichstandard" shows which chip sizes were available in the U1500/U1525 system and in which housing types they were available.
(https://www.richis-lab.de/images/logic/35x07.jpg)
The ceramic housing is easy to open.
(https://www.richis-lab.de/images/logic/35x08.jpg)
The picture above shows the die of the U1525FC007 and is available in original size (34MB): https://www.richis-lab.de/images/logic/35x08XL.jpg (https://www.richis-lab.de/images/logic/35x08XL.jpg)
(https://www.richis-lab.de/images/logic/35x10.jpg)
There are no inscriptions or symbols on the die. Only on the lower edge are the inscriptions of auxiliary structures visible in the remains of the milling line.
(https://www.richis-lab.de/images/logic/35x09.jpg)
The structure of the U1525FC007 is typical for a standard cell architecture. The active elements are lined up in rows. The cells are connected between the rows via a polysilicon layer for vertical lines and within a metal layer for horizontal lines. The supply voltage is fed in at the side. If circuit parts that are further apart need to be connected to each other, the area between the standard cell rows and the bond frame can be used. This is also where the lines run between the interfaces in the bond frame and the inner circuit parts.
However, the standard cell ASICs did not necessarily have to adhere to this clear architecture. In the U1500PC050, the circuit parts are arranged more individually and have been supplemented with very individual structures: https://www.richis-lab.de/phone03.htm (https://www.richis-lab.de/phone03.htm)
(https://www.richis-lab.de/images/logic/35x05.jpg)
The document "Applicative Information 4/88" describes how standard cell ASICs were developed. Once the user has defined his logic circuit, the placement and connection of the cells can be done automatically.
(https://www.richis-lab.de/images/logic/35x06.jpg)
According to "Applikative Information 4/88", in the U1500/U1520 system you can choose from a catalog of 43 standard cells. There is a standard cell catalog from which one page is shown. Unfortunately, the complete catalog is not publicly available.
Each standard cell has a name, here "ANO 24". In the top right-hand corner you can see in which process this cell is available. Below this is the associated symbol, the mathematical description and a textual description of the behavior. When designing the layout, the standard cells are represented by rectangles with the respective symbol. The entire layout is divided into grids. The standard cell shown here takes up 7x5 or 8x5 grid cells. The description of the cell shows which interfaces are available at the top and bottom edges.
The gate equivalent makes it possible to estimate the area required for the circuit. A gate is assumed to have four transistors. Accordingly, the ANO 24 gate requires the area of eight transistors.
Finally, the lower section contains the parasitic capacitances of the inputs and the permissible capacitive load of the output. These figures give the maximum permissible number of gates that can be connected to an output. Line capacitances must be added too. The values apply to the typical operating frequency of 4MHz, at lower frequencies, more gates may be connected to an output. The upper limit is 50 gates. The delay of the cell is also defined.
(https://www.richis-lab.de/images/logic/35x11.jpg)
An early standard cell catalog from 1983 is publicly available on the website of Dr. G. Heinz. However, this catalog only documents the possibilities of the U1500 ASICs based on the CSGT2/N process: http://www.gheinz.de/publications/berliner_ics/index.htm#35 (http://www.gheinz.de/publications/berliner_ics/index.htm#35)
The description of the cells is somewhat more detailed in some cases. The first page contains both a circuit diagram and the gate width of the transistors. The second page shows the corresponding structures as found on the die.
This document also states that it was possible to define new standard cells. The new cells must then be agreed with the publishers.
(https://www.richis-lab.de/images/logic/35x17.jpg)
The layout data for the U1520PC201, another U1520 variant, can be found on Dr. G. Heinz's website: http://www.gheinz.de/publications/berliner_ics/index.htm#slic-b (http://www.gheinz.de/publications/berliner_ics/index.htm#slic-b)
The standard cells are shown as rectangles with the corresponding symbols. The labeled inputs and outputs can be found at the upper and lower edges. The elements have different widths. Flip-flops are slightly higher than standard gates. The necessary input and output blocks are located in the bond frame. Between them, lines in the polysilicon layer and in the metal layer provide the necessary connections.
(https://www.richis-lab.de/images/logic/35x12.jpg)
In the real circuit, the cells are much harder to make out, but with a little practice you can easily recognize the transitions from one cell to the other.
(https://www.richis-lab.de/images/logic/35x13.jpg)
The standard cell catalogue is only available for the CSGT2/N process. Although the CSGT2/S process offers almost the same standard cells, the structures are clearly different. If you know which cells to compare, you can recognise some similarities in a direct comparison. However, this is not sufficient for a simple identification of the cells. For this reason, it is necessary to understand the function of each individual cell. However, knowledge of the basic technology and the logic blocks available is very helpful.
(https://www.richis-lab.de/images/logic/35x20.jpg)
The CSGT2/N standard cell catalog shows the masks used. There are 10 masks listed, but the n+ channel stopper was not necessary, as Dr. G. Heinz explained in detail in 1985: http://www.gheinz.de/publications/berliner_ics/index.htm#18 (http://www.gheinz.de/publications/berliner_ics/index.htm#18)
This results in the 9 masks already described for a relatively simple CMOS process. When looking at the gates, it is immediately apparent that the U1520 is more complex. A second polysilicon layer can be recognized. This matches the 12 customized masks attributed to the U1520 system. This would be a mask to structure the second polysilicon layer. One mask for the contacts to the layer below and one mask for the contacts to the layer above.
(https://www.richis-lab.de/images/logic/35x14.jpg)
The supply lines are located above and below the logic lines in the metal layer. The metal layer (blue) is mainly used for the power supply and signal forwarding between the standard cells. However, it is also partially used within the cells.
The second polysilicon layer added in the CSGT2/S process is only used inside the standard cells (green). It enables the higher integration density and explains the significantly different architecture compared to the U1500. The frame color of the arrows shows on or under which layer the respective layer is located at this point. The visual appearance often changes.
The lower polysilicon layer (pink) is somewhat more finely structured than the upper one. It also represents the gate electrodes. The lower polysilicon layer also provides the contacts to the wiring area. The structures of the polysilicon layers can be seen reasonably well through the metal layer. However, if the edges of the two polysilicon layers cross underneath the metal layer, it is often difficult to identify the conductor routing.
The active areas (white) are located under the other structures. The corresponding edges are clearly visible. At these points, windows have been etched into the thick silicon oxide that otherwise covers the entire wafer ("field oxide"). Transistors only form in these windows when a strip of the lower polysilicon is applied to them.
The active area and the three wiring layers cannot be connected to each other at will. The contacts between the second polysilicon layer and the active area (red) and between the first and second polysilicon layers (orange) are clearly visible. The metal layer can obviously only contact the second polysilicon layer (yellow). If you want to contact the first polysilicon layer or the active area with the metal layer, this must be done via the second polysilicon layer. This sometimes results in contacts that lie on top of each other and areas that appear more complicated than they should be at first glance.
(https://www.richis-lab.de/images/logic/35x15.jpg)
The active areas are always divided into at least two parts. In the upper areas only p-channel MOSFETs are located (red frame). In the lower areas only n-channel MOSFETs can be found (blue frame). The active areas are connected at several points with Vss (blue areas) and Vdd (red areas). In this cell, the Vss contact in the lower left corner is somewhat unclear. This is due to the extended use of the second polysilicon layer. The rectangular contact connects the metal layer with the second polysilicon layer. This then extends to the right and upwards and is connected to two surfaces of the active area via two round contacts.
In the image on the right, the surfaces of the first polysilicon layer are marked in color. Common potentials have the same color. Where the polysilicon covers the active areas, a transistor is formed. The different contact possibilities at the top and bottom edges of the standard cell are clearly visible.
The connections via the second polysilicon layer and the metal layer are marked with dashed lines. Approximately in the middle of the cell there is an area where it is very difficult to assign the contours ("?"). At such points, you have to work with the background knowledge of existing logic functions or record parts of the circuit in order to be able to draw conclusions about the rest.
(https://www.richis-lab.de/images/logic/35x16.jpg)
With the knowledge of the structure and function of the structures, you can finally mark the transistors. Recognizing the circuit is easier than it appears at first glance. Firstly, it is known which logic gates must be present and secondly, the circuits usually only consist of relatively simple parallel and series connections of transistors.
This is an EXOR gate containing five p-channel and five n-channel MOSFETs. The circuit diagram is taken from the standard cell catalog of the U1500. Proper documentation of the standard cells and their contacts is extremely important for further analysis of the circuit.
https://www.richis-lab.de/logic27.htm (https://www.richis-lab.de/logic27.htm)
:-/O
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I have updated the first part of the U1525FC007:
- I have flipped some of the pictures so we have Vss in the lower areas of the pictures and Vdd in the upper area of the pictures. That is probably more convenient for everybody.
and
- I have added a comparison picture with the layout shown in the CSGT2/N standard.
The upper Post is updated due to hotlinking and editing... :-/O :)
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I have updated the first part of the U1525FC007:
- I have flipped some of the pictures so we have Vss in the lower areas of the pictures and Vdd in the upper area of the pictures. That is probably more convenient for everybody.
and
- I have added a comparison picture with the layout shown in the CSGT2/N standard.
The upper Post is updated due to hotlinking and editing... :-/O :)
Very interesting information ! Thanks for sharing.
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(https://www.richis-lab.de/images/logic/35x21.jpg)
Basis for analysing the standard cells used in the U1525FC007 is the list in the document "Applicative Information 4/88". The relatively old standard cell catalogue for the U1500 represents only a subset of the available cells, but it is helpful because it also contains the circuitry of the respective cells. In the U1525FC007, 21 different gate types and 3 interface blocks were used.
(https://www.richis-lab.de/images/logic/35x22.jpg)
The negator or inverter, NEG1, is the simplest gate. It merely inverts the input signal. This behaviour is self-evident if the input signal is used to control a push-pull stage consisting of a p-channel MOSFET (red) and an n-channel MOSFET (blue).
As only two transistors are required, the corresponding cell on the die is very narrow. The input signal contacts a polysilicon strip that runs across two active areas. On the right, these are connected to the supply potentials. On the left-hand side, the second polysilicon layer contacts both transistors and the output signal generated there is led out upwards and downwards. A small metal contact would also make it possible to tap the output signal in the cell via the metal layer. Such metal contacts, which could be used to connect the various gates, can be found in many standard cells. However, they are never used in the U1525FC007.
In his 1985 lecture, Dr G. Heinz explains that in the CSGT2/N process, a connection between the polysilicon and the active area is only possible via a metal island. (http://www.gheinz.de/publications/berliner_ics/index.htm#18 (http://www.gheinz.de/publications/berliner_ics/index.htm#18)) Of course, this could also have been the case with the CSGT2/S process of the U1525-FC007 and would then be an explanation for the unused metal contacts. However, the circuits and the associated layouts show that, as described, the metal layer can contact the upper polysilicon layer and the upper polysilicon layer then contacts the lower polysilicon layer or the active area.
(https://www.richis-lab.de/images/logic/35x23.jpg)
The clocked inverter bears the abbreviation NGT. It is an inverter that is extended upwards and downwards with additional transistors. The additional transistors use the clock signal to control the forwarding of the signal. Like most clock-controlled gates, the clocked inverter also requires a complementary clock signal in addition to the clock signal.
The real implementation is more complex, but still clear. Here too, the output signal is also applied to a small metal island located in the centre of the cell.
(https://www.richis-lab.de/images/logic/35x24.jpg)
The TRIS cell is an auxiliary circuit that is used to control outputs that also enable a tristate state. It is a combination of an inverter, a NAND and a NOR gate. If a high is present at control input Z, output AP remains high and output AN remains low regardless of the status at signal input E. Otherwise, the outputs pass on the current level of the signal input. In this cell, the metal layer is used more often, which makes it much more confusing.
(https://www.richis-lab.de/images/logic/35x25.jpg)
In the ANO24 cell, two AND gates are combined with an OR gate. Here too, the output potential is additionally connected to a metal island within the cell.
(https://www.richis-lab.de/images/logic/35x26.jpg)
In the ANO4 cell, an AND and an OR gate are combined with a NOR gate.
(https://www.richis-lab.de/images/logic/35x27.jpg)
(https://www.richis-lab.de/images/logic/35x28.jpg)
(https://www.richis-lab.de/images/logic/35x29.jpg)
(https://www.richis-lab.de/images/logic/35x30.jpg)
The NAND gates NA2, NA3, NA4 and NA6 are very clearly structured. The variant with six inputs is only available for the NAND gates, not for the NOR gates.
(https://www.richis-lab.de/images/logic/35x31.jpg)
An EXOR gate requires a relatively large number of transistors compared to a NOR gate.
(https://www.richis-lab.de/images/logic/35x32.jpg)
The ONA24 provides the user with a further gate combination. In this case, there are two OR gates that are combined via a NAND gate.
(https://www.richis-lab.de/images/logic/35x33.jpg)
The ONA3 is a simpler gate combination. This is an OR gate that is surrounded by a NAND gate.
(https://www.richis-lab.de/images/logic/35x34.jpg)
(https://www.richis-lab.de/images/logic/35x35.jpg)
(https://www.richis-lab.de/images/logic/35x36.jpg)
Like the NAND gates, the NOR gates are very clear.
(https://www.richis-lab.de/images/logic/35x47.jpg)
The ES block is a simple input that behaves like an inverter. With the ESH and ESL blocks, there are additional inputs that also forward a defined signal in the unconnected state.
There is a protection circuit at the bondpad, consisting of a diode to the Vdd potential and a diode to the Vss potential (pink/green). A strip of the active area forms a resistor that serves as a current limiter (yellow).
On the right are the p-channel and n-channel MOSFETs, which act as inverters for the input buffer. It is interesting to note that the n-channel MOSFET is twice as large as the p-channel MOSFET. This is unusual. The p-channel MOSFET is usually larger because it has poorer properties.
(https://www.richis-lab.de/images/logic/35x48.jpg)
The simple push-pull output is labelled AS1. To the right and left of the bondpad is a whole row of p-channel and n-channel MOSFETs, which can provide the necessary current delivery capability.
(https://www.richis-lab.de/images/logic/35x49.jpg)
The BDL interface is bidirectional and offers a tristate state. For this purpose, the gates of the large output transistors are led out individually. They are usually controlled via the TRIS cell.
A line also leads from the bondpad to the input circuit in the upper area. The familiar protective structures are integrated on the right and left. The transistors of the buffer inverter are located between them. Here too, the n-channel MOSFET is surprisingly large. The L stands for the fact that the block outputs a low level when the input is not connected. An additional p-channel MOSFET is integrated for this purpose, whose gate is connected to the Vss potential and thus represents a pull-up resistor at the input.
(https://www.richis-lab.de/images/logic/35x37.jpg)
(https://www.richis-lab.de/images/logic/35x38.jpg)
The DFFR cell is a master-slave D flip-flop with reset input. The circuit consists of 12 p-channel and 12 n-channel MOSFETs and occupies a correspondingly large area. All master-slave flip-flops are slightly higher than the normal gates to enable a sensible arrangement of the elements.
Here, both the output signal and the complementary output signal, as well as the clock signal and the complementary clock signal can be contacted via the metal layer in the centre of the cell. The lines were also routed to the side edges, presumably to enable simple cascading. These contacts were never used in the U1525FC007.
(https://www.richis-lab.de/images/logic/35x39.jpg)
(https://www.richis-lab.de/images/logic/35x40.jpg)
The master-slave D flip-flop with set and reset input, DFFRS, is the largest standard cell found in the U1525FC007. The circuit does not quite correspond to the circuit diagram. However, the differences are hardly relevant. As in the DFFR cell, the transistors connected to the clock signal are located on the outside, near the supply potentials.
(https://www.richis-lab.de/images/logic/35x41.jpg)
(https://www.richis-lab.de/images/logic/35x42.jpg)
The master-slave D flip-flop with set input, DFFS, is very similar to the DFFR cell.
(https://www.richis-lab.de/images/logic/35x43.jpg)
The LFF cell is a simple D flip-flop. In contrast to the master-slave flip-flops, the normal cell height is sufficient here.
(https://www.richis-lab.de/images/logic/35x44.jpg)
A simple D flip-flop with set input is also available under the designation LFFS.
(https://www.richis-lab.de/images/logic/35x45.jpg)
The RSNA cell is an RS flip-flop. It is an interconnection of two NA2 gates.
(https://www.richis-lab.de/images/logic/35x60.jpg)
Some of the standard cells have been additionally mirrored.
(https://www.richis-lab.de/images/logic/35x46.jpg)
The U1525FC007 contains 1.001 gates using a total of 6.902 transistors. Excluding the gates in the bond frame, 935 gates were used.
https://www.richis-lab.de/logic28.htm (https://www.richis-lab.de/logic28.htm)
:-/O
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(https://www.richis-lab.de/images/logic/35x50.jpg)
There is no datasheet for the U1525FC007. The module was specially developed for the Robotron A5105 educational computer. A circuit diagram of this computer system can be found on Ulrich Zander's website: https://www.sax.de/~zander/bic/bic_hw.html (https://www.sax.de/~zander/bic/bic_hw.html) This allows you to recognise the approximate functionality of the pins and the circuit.
(https://www.richis-lab.de/images/logic/35x51.jpg)
The freeware Inkscape is ideal for analysing the U1525FC007. It allows you to conveniently place and manage a large number of symbols and texts on the die.
(https://www.richis-lab.de/images/logic/35x52.jpg)
In the first step, the bondpads are labelled with the pin designations from the circuit diagram.
(https://www.richis-lab.de/images/logic/35x54.jpg)
(https://www.richis-lab.de/images/logic/35x53.jpg)
In the second part of the documentation, all gate types were identified. Ideally, all gates should be marked on the die in this step. Here, a square was placed around each gate. Inkscape links a consecutive number to the square. The different colours stand for different gate types. If you create folders for the different gate types, this will make it easier to find them later.
(https://www.richis-lab.de/images/logic/35x55.jpg)
The next step is to mark all signals that arrive at the U1525FC007 or are transmitted to the outside. Different colours and collective folders also provide a better overview here. This preparatory step is not absolutely necessary, but it makes it easier to analyse the circuit further.
Prominent signals can be marked one or two levels deeper in the circuit. For example, the reset signal passes through several inverters, partly to distribute the capacitive load of the many receiver gates and partly to generate an inverted signal. The display of a double inversion appears unnecessary at first glance, but indicates that this signal is slightly delayed compared to the original signal.
(https://www.richis-lab.de/images/logic/35x56.jpg)
The die marked in this way serves as the basis for further analysis of the circuit.
(https://www.richis-lab.de/images/logic/35x58.jpg)
Various programmes can be used to document the circuit. KiCad was used here. KiCad is actually used to create circuit board layouts. I think everybody here knows it. ;) However, the circuit diagram editor is also suitable for documenting logic circuits. The 24 standard cells of the U1525FC007 must first be added to the component library.
Minor peculiarities, such as the descending numbering of the inputs on the NOR gates, resulted from initial errors in the analysis, which only became apparent after the circuit diagram was created. In order to keep the change effort within reasonable limits, such cosmetic peculiarities were accepted.
(https://www.richis-lab.de/images/logic/35x59.jpg)
KiCad numbers the gates automatically. This designation is used in Inkscape as the name for the corresponding rectangle. This allows you to find a gate in Inkscape later. It is also easy to see which gates have already been included in KiCad. In addition you can fill the rectangles with 50% transparency black. This makes it easier to analyse because you can immediately see whether a line leads to a known gate.
The fully marked SVG file is stored here (174MB): https://www.richis-lab.de/images/logic/35x57.svg (https://www.richis-lab.de/images/logic/35x57.svg)
(https://www.richis-lab.de/images/logic/35x63.jpg)
The circuit is best recorded from interfaces whose downstream functions are known or at least can be surmised. If, after a certain amount of time, you can't get a feeling for how the local part of the circuit is developing, you should switch to another part of the circuit. When documenting the circuit, you will gradually gain an understanding of how it works and you can arrange and group the gates in KiCad in a sensible way.
https://www.richis-lab.de/logic29.htm (https://www.richis-lab.de/logic29.htm)
:-/O
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(https://www.richis-lab.de/images/logic/35x62.jpg)
The interfaces of the U1525FC007 can be extracted from the circuit diagram of the Robotron A5105 educational computer. The module is connected to the 8Bit wide data bus and receives the clock signal and the reset signal, which is also used by the processor. The processor is a U880, which is functionally equivalent to a Z80. The U1525FC007 receives some control signals directly from the processor, from which it generates the MWAIT signal, among other signals. Nine address lines are processed from the 16-bit wide address bus. The module checks the keyboard or joysticks and generates the sound. The U1525FC007 also supports the U880 in the selection of various function groups: ROM, RAM, optional plug-in cards, PIO and CTC module, graphics unit and an optional cassette drive.
(https://www.richis-lab.de/images/logic/35x61.jpg)
The papers presented at the 13th Microelectronic Components Symposium (Volume 7) contain some information on the U1525FC007. There the designation U1520-FC-007 is used, in which the chip size is missing. In addition to the abbreviation SVG, the component is also described as a "circuit for memory management and sound generation". The printed block diagram matches the integration in the Robotron A5105.
Like the Z80, the U880 can control a maximum memory volume of 64kB. The U1525FC007 extends the address table. The Robotron A5105 contains two EPROMs with a volume of 32kB and 8kB. There are also two DRAM modules, each with 32kB. The memory can be expanded using plug-in cards. The Microelectronic Components Symposium mentions 256kB of RAM. It is more plausible that the memory area can be expanded to a total of 256kB. The RAM may then be a maximum of 192kB in the A5105.
(https://www.richis-lab.de/images/logic/35x63.jpg)
The logic in the U1525FC007 has been completely transferred to a KiCad circuit diagram. The use of only one sheet simplifies the creation of the logic circuit, as you can work more creatively. In addition, there are very large circuit blocks, the division of which would have an unfavourable effect on clarity. The thick blue frames represent a demarcation of self-contained function blocks. The block diagram from the 13th Microelectronic Components Symposium was not yet available here, which is why the layout of the circuit is not based on it. However, the block diagram is fully consistent with the extracted functions.
The KiCad file can be downloaded here: https://www.richis-lab.de/images/35x64.kicad_sch (https://www.richis-lab.de/images/35x64.kicad_sch) (2MB). Such large graphics cannot be packed into common image formats such as JPEG. An SVG file is available here: https://www.richis-lab.de/images/35x83.svg (https://www.richis-lab.de/images/35x83.svg) (14MB). It can be opened and edited in Inkscape.
The following relationships and functions have been extracted and documented as good as possible. However, it is quite possible that minor errors have crept in, individual addresses are not quite correct or potentials have been inverted.
(https://www.richis-lab.de/images/logic/35x64.jpg)
Some interfaces can be used as a starting point for the documentation of the circuit. These include the address bus, for example. The global identifiers outlined in red are the interfaces to the outside, i.e. the bondpads. Internally, most connections are shown as continuous lines. Only some highly branched potentials, such as the address bus, are distributed on the circuit diagram with so-called hierarchical identifiers. The address bus first passes through the input gates. Most address lines are also inverted for further use.
Further global signals are collected on the right, for example the read and write signals. The reset signal serves a total of 55 gates. The large number is probably one reason why five inverters pre-process the signal. The clock signal only serves seven gates, yet three inverters have been integrated here. The requirements for signal integrity were probably higher than for other signals. In the Robotron A5105, the PM potential is connected to the 5V potential via a pull-up resistor. The function of this potential will be considered in more detail later.
(https://www.richis-lab.de/images/logic/35x65.jpg)
The data bus is routed to bidirectional interface gates with tristate function. These interface gates are controlled via TRIS gates. The /OUT_EN signal controls whether data may be placed on the data bus or whether the current potentials are to be read in. Clocked inverters are used to read in the data. An internal data bus is generated from this circuit.
(https://www.richis-lab.de/images/logic/35x66.jpg)
A function block controls the addressing of the memory areas. SL0L and SL0H each activate one of the two EPROM modules. S1 and S3 can be used to select the two interfaces for optional modules. The selection of the two 32kB RAM modules is controlled via CAS and WSMUX. Everything is controlled via the internal control signals S1 and S2.
The second function block generates a whole series of control signals based on the address lines and the control signals of the U880. In addition, the interrupt output of the PIO module is analysed. The read and write signals for the graphics unit, which also serve as selection signals, are output directly. The selection signals for PIO and CTC are also output directly. The DIR signal defines the flow direction of the data transceiver at the connectors for the optional modules. The WAIT signal is used to signal to the processor when the addressed resource is available.
The right-hand function block also generates some internal control signals. One of these enables data to be transferred to the data bus. Further control signals can be used to transfer data to the internal registers. In the presentation from the Microelectronic Components Symposium, two of the registers are labelled Port A and Port C. Port A is written in parallel. Port C can be written in parallel or serially via two control signals. The integrated sound generator has very extensive configuration options. The register to be written to is selected via a control signal. A second control signal can then be used to write to this register.
(https://www.richis-lab.de/images/logic/35x67.jpg)
The control signals SL0L, SL0H, SL1, SL3, WSMUX and CAS are selected by linking the internal control signals S1 and S2 with the control signals of the processor. S0L and SL0H are also dependent on address bit A15.
WSMUX and CAS also have flip-flops which ensure that the address of the processor is split into row and column selection. If MRQ is active, the RAM immediately takes half of the address as row selection. If the RAM is selected, the circuit in the U1525FC007 ensures that the second half of the address is switched through to the RAM with WSMUX and this part is subsequently adopted as column address with CAS.
At first glance, it seems strange that the row selection in the RAM always takes place, even if the RAM is not selected at all. This transparency is necessary so that the DRAM can be refreshed, which the U880, like the Z80, carries out automatically. As the DRAM only outputs data on the bus with a column address, the selection of a row address alone does not lead to a bus collision.
(https://www.richis-lab.de/images/logic/35x70.jpg)
(https://www.richis-lab.de/images/logic/35x68.jpg)
The decoding of the control signals is quite clear. The links between the addresses and the control signals can be easily extracted. While MRQ indicates an access to the memory area, the processor uses IORQ to communicate an access to a peripheral circuit. The signal M1 belongs to such an interrupt cycle.
(https://www.richis-lab.de/images/logic/35x71.jpg)
The generation of the DIR and MWAIT signals can be seen here. The U1525FC007 only inserts a fixed delay between the start of a memory interaction and the positive feedback via MWAIT.
(https://www.richis-lab.de/images/logic/35x72.jpg)
The Port A register can be used to configure the addressing of the memory areas. The current value of the data bus is saved in port A with the corresponding control signal. The stored value can also be read out.
Depending on which of the eight bits are set in port A, different combinations of address bits 14 and 15 are required to activate the control signals S1 and S2. Various combinations do not make sense. In all probability, only two bits are ever set in port A. Combinations that activate S1 and S2 with the same address combination also appear to make little sense and are painted grey here.
(https://www.richis-lab.de/images/logic/35x73.jpg)
The Port A register is build with DFFR flip-flops.
(https://www.richis-lab.de/images/logic/35x69.jpg)
To be able to select a memory area, RFSH must have a high level and MRQ a low level. This means that there is no refresh cycle active and the processor wants to access a memory. The control signal combinations 01 and 11 can be used to select the interfaces of the optional plug-in cards (SL1/SL3). 10 activates WSMUX / CAS and thus the interface of the RAM modules.
SL0L and SL0H, the two EPROM modules, are only active if no bit is set in the Port A register. This appears illogical at first glance, as no other memory area can be activated in this state. Port A must first be rewritten. However, this implementation has the advantage that the EPROMs where the program is located can be accessed immediately after a reset without initialising the SVG. By linking to address bit 15, the control of the EPROM initially appears completely transparent to the processor.
(https://www.richis-lab.de/images/logic/35x74.jpg)
A multiplexer makes it possible to place various data on the data bus. One data source is the TB* inputs, which show the processor which key on the keyboard is pressed. Alternatively, the data in the Port A or Port C registers can be placed on the data bus. One of the three data sources is selected via the address lines A0 and A1.
The data register Port C can be loaded with data in parallel or serially. The content of the register controls the line selection of the keyboard logic (TA*), the cassette recorder, the caps lock LED and the signal for the key tone.
(https://www.richis-lab.de/images/logic/35x75.jpg)
Here you can see a part of the multiplexer.
(https://www.richis-lab.de/images/logic/35x76.jpg)
The Port C register is constructed with DFFRS flip-flops. The register can be loaded in parallel via the D inputs. Serial loading takes place via the set and reset inputs. The underlying logic evaluates the level of data bit 0. Data bits 1 to 3 define which bit of the register is to be written.
(https://www.richis-lab.de/images/logic/35x77.jpg)
The sound generator takes up a lot of space in the U1525FC007. The configuration registers account for a large proportion of this. There are 16 registers with a total of 83 bits.
(https://www.richis-lab.de/images/logic/35x79.jpg)
The sound generator integrated in the U1525FC007 is very similarly to the AY-3-8910 sound generator from General Instrument. Even the control registers have the same structure and arrangement. The U1525FC007 only lacks the Port A and Port B interfaces and the mixer at the output mixes the signals into a single channel. In addition, the digital-to-analogue converter is located externally.
(https://www.richis-lab.de/images/logic/35x78.jpg)
Four LFFS flip-flops use the first four bits of the data bus to select a line of the configuration register for the sound generator.
(https://www.richis-lab.de/images/logic/35x80.jpg)
With some additional logic, the LFFS flip-flops generate the clock signals for LFF flip-flops, which represent the configuration registers themselves. The inputs are connected to the data bus. One address triggers the LFFS flip-flops and thus the line selection. Another address then allows the LFF flip-flops to accept the data on the data bus.
(https://www.richis-lab.de/images/logic/35x81.jpg)
The sound generator is based on six clock dividers. The 3,75 MHz basic clock of the A5105 can first be divided down by a factor of 16 before it is then passed to the five other clock dividers as a working clock.
One clock divider defines the basic frequency of the noise generator and can divide the working clock by 2 to 2^5. A further clock divider generates the clock for the amplitude modulation with a divider factor of 2 to 2^17. The three tones that the sound generator can supply are generated via three clock dividers, each with a divider factor of 2 to 2^13. This results in a frequency range from 28Hz to 117kHz.
(https://www.richis-lab.de/images/logic/35x82.jpg)
The clock dividers are based on DFFRS flip-flops. Their exact mode of operation only becomes apparent at second glance. The circuit not only takes up a lot of space on the circuit diagram, but also on the die.
The interfaces PM, OP0, OP1, OP2 and OP3 appear to be used for diagnostic purposes. The frequency dividers of channels A, B, C and the envelope generator are divided into groups of six and one group of four. This results in nine groups that can be read out individually. The selection signal for register 0010 switches the four OP outputs, making it possible to reach eight of the nine groups. The PM input can be used to isolate the groups from each other and feed them with the same clock signal. The PM signal also switches the remaining group to the S0H output.
(https://www.richis-lab.de/images/logic/35x83.jpg)
The sound generator contains a noise generator that also uses a divided clock frequency.
(https://www.richis-lab.de/images/logic/35x84.jpg)
Of course, this is only a pseudo-noise generator that does not really generate random noise. There are 20 DFFS flip-flops connected in series. The input signal is generated by an EXOR gate, which links the current output signal with the output signal of the third flip-flop. This results in a pseudo-random output signal.
(https://www.richis-lab.de/images/logic/35x85.jpg)
The envelope, i.e. the amplitude modulation of the output signal, can be defined with a further circuit section. The basis here is also the divided working clock.
(https://www.richis-lab.de/images/logic/35x86.jpg)
The datasheet of the AY-3-8910 shows which envelopes can be generated. The circuit itself is rather confusing. It feeds four data lines, the value of which represents the current amplitude.
(https://www.richis-lab.de/images/logic/35x87.jpg)
The configuration register ultimately defines which of the three tones is forwarded. Each tone can be linked to the noise signal or just the noise signal can be forwarded. The three signals then pass through an amplitude control, which can be set via the configuration register and is also modulated with the generated envelope function.
(https://www.richis-lab.de/images/logic/35x89.jpg)
Here you can see the circuit for one channel. The tone or the noise signal or both signals are selected in gate U817. The NOR gates on the far right pass on the signal if the ANO24 gates in front of them allow this. The amplitude configuration and the envelope information are linked in these gates. The four outputs all carry the same signals when they are active. Depending on which of the outputs are active, different amplitudes will result later.
(https://www.richis-lab.de/images/logic/35x90.jpg)
The functionality of the sound output becomes clearer if you take a look at the circuit diagram of the A5105. There, a resistor chain represents a discrete DAC. Each S output serves an inverter, which influences the output level more or less depending on the connection point.
(https://www.richis-lab.de/images/logic/35x88.jpg)
Before the sound signal is delivered, a mixer combines the three generated channels.
https://www.richis-lab.de/logic30.htm (https://www.richis-lab.de/logic30.htm)
:-/O
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FYI - a silicon-on-sapphire die..
https://www.righto.com/2023/12/HP-silicon-on-sapphire-phi-chip.html (https://www.righto.com/2023/12/HP-silicon-on-sapphire-phi-chip.html)
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Yeah, that´s cool. I have an old and very special HP die here and thought it was SoS too. It had a strange colour but unfortunately it´s not SoS. :(
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(https://www.richis-lab.de/images/logic/36x01.jpg)
(https://www.richis-lab.de/images/logic/36x02.jpg)
Four NAND gates, each with two inputs, are integrated in the D100. It corresponds to the 7400. The D100 belongs to the D1** logic family, which was produced at the Halbleiterwerk Frankfurt Oder. The component above lacks professional labeling. It comes from a so-called "Bastlerbeutel" (hobbyist's bag). The hobbyist bags were used to sell components that did not meet the specifications but were basically functional.
The integrated circuit corresponds to the familiar concept. The input transistor links the two input signals. This is followed by a driver transistor, which generates the two control signals for the output stage. Finally, there is a push-pull output stage at the output. The 7400 from Texas Instruments (https://www.richis-lab.de/logic14.htm (https://www.richis-lab.de/logic14.htm)), the D200 (https://www.richis-lab.de/wafer01.htm (https://www.richis-lab.de/wafer01.htm)) and the K155LA3 (https://www.richis-lab.de/logic11.htm (https://www.richis-lab.de/logic11.htm)) have protective diodes at the inputs. These are not initially integrated in the D100.
(https://www.richis-lab.de/images/logic/36x03.jpg)
The dimensions of the die are 1,5mm x 1,3mm. There are structures in three corners, which were most likely used to correctly align the masks during production. With these structures the alignment of the various layers can be checked on the finished die afterwards too.
(https://www.richis-lab.de/images/logic/36x04.jpg)
The individual parts of the circuit can be easily identified. The input transistor T1 has two additional, unused emitter surfaces. It can therefore be assumed that the intention was to use a different metal layer to create gates with up to four inputs.
(https://www.richis-lab.de/images/logic/37x01.jpg)
The D100 shown here was manufactured in April 1973.
(https://www.richis-lab.de/images/logic/37x02.jpg)
The die does not differ from the first D100. The color transition in the lower left corner suggests that the thickness of the silicon oxide layer is highly inhomogeneous.
(https://www.richis-lab.de/images/logic/38x01.jpg)
Like the SN8400, the E100 was approved for an extended temperature range of -25°C to 85°C. The numbers I9 stand for production in September 1977.
(https://www.richis-lab.de/images/logic/38x02.jpg)
The die is basically constructed in the same way as the circuits above. However, an additional auxiliary structure was used in the bottom right-hand corner, which is often found in circuits from the HFO. In addition, you can now see the cut-outs in the passivation layer on the bondpads. The protective passivation layer seems to be missing on the D100 from the hobbyist's bag.
(https://www.richis-lab.de/images/logic/38x03.jpg)
The material surrounding the die extends to a bondpad at one point. This is the material used to connect the two housing parts. It is not conductive, even if it looks metallic here.
(https://www.richis-lab.de/images/logic/38x04.jpg)
A closer look reveals a defect in the metal layer. At one point, several small areas of metal were left behind when etching the metal layer. The structure between the two large contacts in the left-hand area is particularly problematic. There is a risk of the supply voltage being short-circuited there.
(https://www.richis-lab.de/images/logic/39x01.jpg)
This E100 was manufactured in November 1977.
(https://www.richis-lab.de/images/logic/39x02.jpg)
Nothing has changed in the design of the circuit.
(https://www.richis-lab.de/images/logic/40x01.jpg)
The D100 shown here was manufactured in December 1978.
(https://www.richis-lab.de/images/logic/40x02.jpg)
The design of the die has not changed, but the auxiliary structures have been modified once again. At the lower edge a bondpad had to be bonded twice.
(https://www.richis-lab.de/images/logic/41x01.jpg)
(https://www.richis-lab.de/images/logic/41x02.jpg)
No new details can be seen on the second D100 from December 1978.
(https://www.richis-lab.de/images/logic/42x01.jpg)
The D100 shown here was produced in March 1979 and was put in an epoxy package.
(https://www.richis-lab.de/images/logic/42x02.jpg)
The die was damaged when the package was opened. However, it is easy to see that the structures have not been modified any further.
(https://www.richis-lab.de/images/logic/43x01.jpg)
The D100 documented here was produced in January 1982.
(https://www.richis-lab.de/images/logic/43x02.jpg)
Unfortunately, the die was badly damaged. However, some interesting details can still be seen. The arrangement of the circuit parts has not changed. However, each input now has a protective diode directly on the respective bondpad. The width of the die can no longer be reconstructed. The height has been reduced slightly to 1,2 mm. The label 02D100 reveals that this is the second revision of the D100 design.
https://www.richis-lab.de/logic31.htm (https://www.richis-lab.de/logic31.htm)
:-/O
-
(https://www.richis-lab.de/images/logic/44x01.jpg)
(https://www.richis-lab.de/images/logic/44x02.jpg)
Like the D100, the D103 contains four NAND gates, each with two inputs. In contrast to the push-pull output of the D100, however, the D103 only has an open collector output. The D103 therefore corresponds to the 7403. The characters WO stand for production in October 1988.
(https://www.richis-lab.de/images/logic/44x03.jpg)
The dimensions of the die are 1,45mm x 1,25mm. The D103 uses the same basic design as the D100. Here, only the metal layer has been adapted so that the highside transistor with its collector resistor and the diode are left out. The label 02D103 in the bottom right-hand corner most probably refers to a second revision. As with the D100 produced in January 1982, protective diodes are also integrated at the inputs. However, the layout of the metal layer on the D103 is noticeably more angular.
(https://www.richis-lab.de/images/logic/44x04.jpg)
Due to the reduced metal layer, some structures can be recognized even better. The diode on the right is constructed like a transistor. It therefore has a double contact. The metal layer contacts both the base surface and the collector surface via this contact.
https://www.richis-lab.de/logic32.htm (https://www.richis-lab.de/logic32.htm)
:-/O
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Going back a bit: great reverse-engineering of the U1525FC007 ASIC. I want to make sure I'm interpreting the amplitude control correctly though, as it seems a bit unusual. It looks like...
- Each audio channel is a single bit (only square-wave output)
- The purpose of the external R-2R ladder is for amplitude modulation only, for each single-bit channel
Nice minimal way to do it with limited resources, normally with amplitude control & DDS I'd imagine needing a hardware multiplier - gets more options for wave shapes though.
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The U1525FC007 was a lot of work but also very interesting and satisfying. ;D
You are right:
- In the first place every channel is a single bit square wave.
- The aplitude control in the chip activates up to four outputs, every output can deliver the square wave of this channel.
- The external resistor ladder is just for amplitude modulation. More active outputs generate more amplitude.
It was a time when they had to achive a lot with very limited resources, especially in the GDR.
-
(https://www.richis-lab.de/images/logic/45x01.jpg)
(https://www.richis-lab.de/images/logic/45x02.jpg)
The D110 contains three NAND gates, each with three inputs. It corresponds to the 7410. The characters KP stand for production in August 1975.
(https://www.richis-lab.de/images/logic/45x03.jpg)
The D110 uses the same basic design as the D100. It is the first, older design. The metal layer has been adapted so that three bondpads each lead to the input transistors with the four emitters. The NAND gate in the bottom left-hand corner has been omitted.
(https://www.richis-lab.de/images/logic/45x04.jpg)
An unused transistor of the lower left gate was equipped with testpads and could thus be used as a test transistor.
https://www.richis-lab.de/logic33.htm (https://www.richis-lab.de/logic33.htm)
:-/O
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(https://www.richis-lab.de/images/logic/46x01.jpg)
(https://www.richis-lab.de/images/logic/46x02.jpg)
The D120 contains two NAND gates with four inputs each. It corresponds to the 7420 logic module. The KM symbol stands for production in August 1972.
(https://www.richis-lab.de/images/logic/46x03.jpg)
The D100, the D103 and the D110 are based on the same basic design. There, the input transistors of each gate have four emitters for up to four inputs. Nevertheless, this basic design was not used for the D120. This allowed to save the area of two unused gates. The edge length of the die is 1,2 mm. The die in the D100 is noticeably larger with 1,5mm x 1,3mm. The design of the gates is very similar to the design in the D100, but the arrangement of the individual elements is slightly different.
(https://www.richis-lab.de/images/logic/46x04.jpg)
The input transistor in the lower gate is destroyed. There was a high current flow between the left two inputs and the upper right input. The high temperatures have left traces on the current path. The metal layer melted around these traces.
(https://www.richis-lab.de/images/logic/47x01.jpg)
This D120 was produced in September 1976.
(https://www.richis-lab.de/images/logic/47x02.jpg)
The circuit design has not changed. However, it is a newer revision. There is now another auxiliary structure in the middle of the lower edge. It is also noticeable that the metal layer in the area of the bondpads looks different. The component obviously has a passivation layer that has been omitted in these areas. The older D120 does not yet have a passivation layer.
https://www.richis-lab.de/logic34.htm (https://www.richis-lab.de/logic34.htm)
:-/O
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The damage looks like the inputs got pulled far apart enough to EBO breakdown one of the inputs (you can see the electromigration track showing up). That looks like it allowed enough current to flow in the forward base-emitter junctions to blow the metal lines.
Always fun trying to figure out what someone did to blow a device up like this!
-
The easy answer is always EOS, electrical overstress.
If you need more information it often gets complicated... :-+ ...and for some people that´s also where the fun starts. 8)
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Been curious about the small differences between the two versions of D120C, and made this animated gif to visually compare the two:
(https://cdn.hackaday.io/images/original/331811735859548221.gif)
Click to enlarge. Posted it small because animated gifs can be annoying.
Since EEVblog turns any animated gifs into a static pic, had to host the gif as a public page on my hackaday.io https://hackaday.io/page/399250-die-pics-of-2-sligtly-different-d120c-2-x-4-inputs-nand-ttl , then embed the animated gif here. (In case hosting the animated gif there is not OK, please let me know so I can delete that page from hackaday.io)
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КМ555ИР8
KM555IR8
(https://images.vfl.ru/ii/1696630030/5b891359/39028435_m.jpg) (https://vfl.ru/fotos/5b89135939028435.html)
(https://images.vfl.ru/ii/1696630032/3fe632fe/39028436_m.jpg) (https://vfl.ru/fotos/3fe632fe39028436.html)
(https://images.vfl.ru/ii/1696630034/1ae696e3/39028437_m.jpg) (https://vfl.ru/fotos/1ae696e339028437.html)
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Do you know what the function is? It looks like there's 8 identical sections, chained together in some sort of way. Maybe a shift register?
Edit: Yep, running this through a translator says 8-bit shift register, with parallel outputs: https://eandc.ru/catalog/k555ir8/ (https://eandc.ru/catalog/k555ir8/)
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This is an eight-bit serial shift register with parallel outputs.
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1109КТ13
4-channel current switch
(https://images.vfl.ru/ii/1696971199/e664546d/39033428_m.jpg) (https://vfl.ru/fotos/e664546d39033428.html)
(https://images.vfl.ru/ii/1696971200/4d766819/39033429_m.jpg) (https://vfl.ru/fotos/4d76681939033429.html)
(https://images.vfl.ru/ii/1696971202/679ca8ed/39033430_m.jpg) (https://vfl.ru/fotos/679ca8ed39033430.html)
(https://images.vfl.ru/ii/1696971485/d468ba4b/39033431_m.jpg) (https://vfl.ru/fotos/d468ba4b39033431.html)
(https://images.vfl.ru/ii/1696971486/d7b43e90/39033432_m.jpg) (https://vfl.ru/fotos/d7b43e9039033432.html)
(https://images.vfl.ru/ii/1696971487/93db5ebf/39033433_m.jpg) (https://vfl.ru/fotos/93db5ebf39033433.html)
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(https://www.richis-lab.de/images/logic/48x01.jpg)
(https://www.richis-lab.de/images/logic/48x02.jpg)
Here you can see a gate array based on ECL, which was used around the CPU of the CDC Cyber C2000. The C2000 belongs to a family of supercomputers. The gate array was manufactured by National Semiconductor. The datecode refers to the year 1991 and, as will be shown later, FD1902 is the designation of the component.
The PGA package has a metal lid on both the top and bottom. The upper metal lid carries the chip and has a metal bolt, which is most likely used to attach a heat sink. The top metal lid is slightly raised. This makes sense with regard to the heatsink, as there are many contact points on the top of the package that would otherwise have to be specially insulated.
(https://www.richis-lab.de/images/logic/48x03.jpg)
(https://www.richis-lab.de/images/logic/48x04.jpg)
If you remove the bottom cover, you can take a look at the die. The dimensions are 11,8mm x 11,6mm. A closer look reveals the very wide supply lines, which form several frames and cover almost the entire surface of the die.
This picture is also available in a higher resolution: https://www.richis-lab.de/images/logic/48x04XL.jpg (https://www.richis-lab.de/images/logic/48x04XL.jpg) (70MB)
(https://www.richis-lab.de/images/logic/48x05.jpg)
The letters FCI, which are shown next to the copyright symbol, could stand for Fairchild Camera and Instruments. Fairchild has been absorbed into National Semiconductors over time.
A test structure can be seen on the upper edge, which apparently documents the resolution of the process in the range between 1,3µm and 0,7µm.
(https://www.richis-lab.de/images/logic/48x06.jpg)
FD1902 appears to be the designation of this part. This character string can also be found on the package.
(https://www.richis-lab.de/images/logic/48x07.jpg)
The meaning of the character string ZB remains open. FGA14K is the designation of the gate array.
(https://www.richis-lab.de/images/logic/48x10.jpg)
The gate array used here is the FGA14000 model. The “National Semiconductor F100K ECL Logic Databook and Design Guide” contains some information on the product family.
(https://www.richis-lab.de/images/logic/48x11.jpg)
The FGA gate arrays were built by National Semiconductor using the ASPECT-II process. ASPECT stands for “Advanced Signal Poly Emitter Coupled Technology”. Background information on this process can be found in the IEEE publication “A 30,000 Gate ECL Gate Array using advanced single poly technology and four level metal interconnect”. According to this, the minimum structure width is 1,5 µm and the wiring is carried out in four metal layers. The sectional view shows one of the bipolar transistors, which offer a ft of 10Ghz.
(https://www.richis-lab.de/images/logic/48x08.jpg)
Several masks are depicted in one corner of the die.
(https://www.richis-lab.de/images/logic/48x09.jpg)
The integrated circuit itself is barely visible. This is not only due to the massive supply lines and the four metal layers, but also to the fact that at least one of the upper insulation layers is almost completely opaque.
https://www.richis-lab.de/logic35.htm (https://www.richis-lab.de/logic35.htm)
:-/O
(https://www.richis-lab.de/images/logic/49x01.jpg)
(https://www.richis-lab.de/images/logic/49x02.jpg)
Like the FD1902, the FD2104 is another ECL gate array used in the CPU of the CDC Cyber C2000. Capacitors have been soldered to the top of the FD2104. Presumably the supply voltage is buffered there.
(https://www.richis-lab.de/images/logic/49x03.jpg)
(https://www.richis-lab.de/images/logic/49x04.jpg)
As with the FD1902, no details of the integrated circuit can be seen. The structures on the surface merely show that it is a different circuit.
This image is also available in a higher resolution: https://www.richis-lab.de/images/logic/49x04XL.jpg (https://www.richis-lab.de/images/logic/49x04XL.jpg) (66MB)
(https://www.richis-lab.de/images/logic/49x05.jpg)
(https://www.richis-lab.de/images/logic/49x07.jpg)
(https://www.richis-lab.de/images/logic/49x08.jpg)
In the corners there are structures known from the FD1902.
(https://www.richis-lab.de/images/logic/49x06.jpg)
The designation of the design here is FD2104.
https://www.richis-lab.de/logic36.htm (https://www.richis-lab.de/logic36.htm)
:-/O
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(https://www.richis-lab.de/images/logic/50x01.jpg)
(https://www.richis-lab.de/images/logic/50x02.jpg)
The D130 contains a NAND gate with eight inputs. It corresponds to the 7430 logic module. The characters N9 stand for production in September 1981.
(https://www.richis-lab.de/images/logic/50x03.jpg)
The D100 (https://www.richis-lab.de/logic31.htm (https://www.richis-lab.de/logic31.htm)), the D103 (https://www.richis-lab.de/logic32.htm (https://www.richis-lab.de/logic32.htm)) and the D110 (https://www.richis-lab.de/logic33.htm (https://www.richis-lab.de/logic33.htm)) are based on the same basic design. A separate design has already been developed for the D120 (https://www.richis-lab.de/logic34.htm (https://www.richis-lab.de/logic34.htm)) in order to save silicon area. The same applies to the D130. A special input transistor with eight emitters was required here. The remaining circuit components are very similar to the other gates. As with the D120, the edge length of the die is 1,2 mm.
(https://www.richis-lab.de/images/logic/51x01.jpg)
The D130 shown here was produced in December 1981.
(https://www.richis-lab.de/images/logic/51x02.jpg)
The die shows no differences to the first die.
https://www.richis-lab.de/logic37.htm (https://www.richis-lab.de/logic37.htm)
:-/O
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Interesting contrasting the layout of these older parts against some newer TTL, just in compactness - here's a 74LS00 and 74LS107, from a hybrid module with a late-90's date code. You can see that by this point, with 7400-series ICs being a commodity item, they were really trying to squeeze the layout as small as possible on the 7400!
(https://live.staticflickr.com/65535/54316414372_27d999111e_c.jpg) (https://flic.kr/p/2qKKPCY)
(https://live.staticflickr.com/65535/54317534829_7ce0c2ba0c_c.jpg) (https://flic.kr/p/2qKRyHc)
(The '107 is also interesting because it has a "73A" written with doping but a "107A" on the metal layer - these are both dual JK-FF parts, and I'd originally thought it was a 74LS73, except that the external connections didn't make sense with its pinout. Makes me wonder if as part of that cost optimization, the manufacturer managed to use most of the same process for both of them, just with different metal layers?)
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It´s really funny to see how much silicon area they used back in the days. Today you can built a high performance mikrocontroller on this area.
The logic families for sure had a high cost pressure.
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Don't want to step on your thread here, but here's some other digital logic I ran across recently, from a mystery hybrid on a Rocketdyne board (https://www.eevblog.com/forum/projects/avionics-teardown-looking-at-some-mystery-rocketdyne-boards/msg5256276/#msg5256276). They all look like SSI/MSI CMOS of some kind.
This one's interesting because the structure looks very "new", as in, taking full advantage of high process resolution. Rather than each transistor (or diode) being a single easily-identifiable source-gate-drain structure, it's a conglomeration of individual tiny devices, kind of like the way modern power MOSFETs are made. At least that's my interpretation - please correct me if I'm wrong:
(https://live.staticflickr.com/65535/54322216302_3f7e97089f_c.jpg) (https://flic.kr/p/2qLgymf)
These two are much more "traditional-looking", but I still have no idea what they are. The 1st has some very large transistors (might be a 4x analog switch actually, like the 4066? Oops), and the 2nd could be a multi-bit register or mux of some kind? It looks like there's a common set of 7 control lines in the center, which run up on the left, loop around at the top, and come down on the right.
(https://live.staticflickr.com/65535/54323340304_78d2fe56c9_c.jpg) (https://flic.kr/p/2qLnjtA)
(https://live.staticflickr.com/65535/54323107051_4e2ca52d9d_h.jpg) (https://flic.kr/p/2qLm88Z)
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Don't want to step on your thread here, but here's some other digital logic I ran across recently, from a mystery hybrid on a Rocketdyne board (https://www.eevblog.com/forum/projects/avionics-teardown-looking-at-some-mystery-rocketdyne-boards/msg5256276/#msg5256276). They all look like SSI/MSI CMOS of some kind.
That´s no problem for me. :-+
This one's interesting because the structure looks very "new", as in, taking full advantage of high process resolution. Rather than each transistor (or diode) being a single easily-identifiable source-gate-drain structure, it's a conglomeration of individual tiny devices, kind of like the way modern power MOSFETs are made. At least that's my interpretation - please correct me if I'm wrong:
To me this part looks more like an analog switch (like this one: https://www.richis-lab.de/aswitch06.htm (https://www.richis-lab.de/aswitch06.htm)).
I wouldn´t say that it is a very modern process but that always depends on what you want to call modern. ;D
The second die could be a analog switch too or it is a gate driver.
The third die is a big analog switch or MUX.
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(https://www.richis-lab.de/images/logic/52x01.jpg)
Texas Instruments always prefixes the designation of its logic components with the letters SN. The letter J is assigned to components that have been developed, manufactured and tested in accordance with the MIL-STD-883 standard. In contrast to the 74 logic, the 54 logic is specified for the military temperature range (-55°C to 125°C). AS stands for “Advanced Schottky”. The numbers 04 show that six inverters have been integrated here. FK stands for the package type.
(https://www.richis-lab.de/images/logic/52x03.jpg)
Texas Instruments explains in “The TTL Data Book Volume 1” the difference between the logic families. The AS variant offers the shortest propagation delays.
(https://www.richis-lab.de/images/logic/52x05.jpg)
(https://www.richis-lab.de/images/logic/52x02.jpg)
The dimensions of the die are 1,4mm x 1,2mm. As usual for Texas Instruments, a Ti logo is shown on the die. In addition, the characters AS04 can be found to match the logic module. Special structures are superimposed in different layers on the bottom and right edges. They clearly show how well the masks were aligned during production.
(https://www.richis-lab.de/images/logic/52x04.jpg)
The SNJ54AS04 uses two metal layers. The active structures are unusual. :o
https://www.richis-lab.de/logic38.htm (https://www.richis-lab.de/logic38.htm)
:-/O
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To me this part looks more like an analog switch (like this one: https://www.richis-lab.de/aswitch06.htm (https://www.richis-lab.de/aswitch06.htm)).
I wouldn´t say that it is a very modern process but that always depends on what you want to call modern. ;D
Yes hah, by "modern" in this case I mean "newer than the 70's"....not actually very modern. And that's an interesting comparison, thanks - although I'm not convinced this one is an analog switch. In your analog switch die, only the actual analog-switch MOSFETs have the "compound" construction, while the other (control logic) MOSFETs are more standard single-piece lateral devices; in my mystery die, it looks like everything (including the ESD diodes) has the "compound" construction.
Every time I look at a die with no part number markings, it just makes me wish harder that there was a die-image-matching search engine.
Also, on that 54AS04, a lot of those alignment markers along the edge don't actually look well-aligned. Do you know if that was a camera/imaging-setup artifact, or intentional, or if the layout can actually tolerate that much slop? (The actual features look better-aligned than that, but I'm not an expert...)
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To me this part looks more like an analog switch (like this one: https://www.richis-lab.de/aswitch06.htm (https://www.richis-lab.de/aswitch06.htm)).
I wouldn´t say that it is a very modern process but that always depends on what you want to call modern. ;D
Yes hah, by "modern" in this case I mean "newer than the 70's"....not actually very modern. And that's an interesting comparison, thanks - although I'm not convinced this one is an analog switch. In your analog switch die, only the actual analog-switch MOSFETs have the "compound" construction, while the other (control logic) MOSFETs are more standard single-piece lateral devices; in my mystery die, it looks like everything (including the ESD diodes) has the "compound" construction.
Hm, I took a second look at the image. Now I don´t think any more it´s an analog switch. It seems these are Highside-/Lowside switches at the output.
Six inputs, eight outputs, the part in the middle looks like an adressing. Perhaps it´s a shift register.
Every time I look at a die with no part number markings, it just makes me wish harder that there was a die-image-matching search engine.
Either this or an AI circuit recognition tool. ;D
Also, on that 54AS04, a lot of those alignment markers along the edge don't actually look well-aligned. Do you know if that was a camera/imaging-setup artifact, or intentional, or if the layout can actually tolerate that much slop? (The actual features look better-aligned than that, but I'm not an expert...)
In my view the alignment is not bad (for the big structures). As far as I know these alignment markers are built like caliper: They should not lay above each other and show a small horizontal misalignment very clearly (vertical on the right).
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(https://www.richis-lab.de/images/logic/53x01.jpg)
(https://www.richis-lab.de/images/logic/53x02.jpg)
The Texas Instruments SN7400 shown here was produced in 1970. It is packaged in a so-called flat package, a metal housing in which the pins are led straight out to the side. One contact has a protruding element that identifies pin 1. The transport frame is known as a Mech-Pak carrier. A piece of Kapton is glued to the underside.
(https://www.richis-lab.de/images/logic/53x04.jpg)
With the different SN5400 and SN7400 variants, it is important to note that the pin assignment is not always the same. Texas Instruments shows this in “The TTL Data Book for Design Engineers - Second Edition”. The SN54L00 in the “flat package” (T), the SN5400 and the SN54H00 in the “ceramic flat package” (W) expect their supply voltage at the pins in the center of the package, not at the opposite corners. In addition, the lower gates are rotated by 180°. The SN7400S contains the right-hand architecture, but is so old that it is no longer mentioned.
(https://www.richis-lab.de/images/logic/53x03.jpg)
Glass insulates the pins from the metal housing. The cover is welded onto the housing.
(https://www.richis-lab.de/images/logic/53x05.jpg)
Inside the package, you can see that the pins on the sides are literally molded in glass.
(https://www.richis-lab.de/images/logic/53x06.jpg)
The dimensions of the die are 1,5mm x 1,3mm. It is therefore significantly larger than the newer generation (https://www.richis-lab.de/logic14.htm (https://www.richis-lab.de/logic14.htm)). Some auxiliary structures are shown in the corners, which make it easier to place the masks appropriately and monitor the manufacturing process.
The design does not yet include protection diodes at the inputs. The input transistors of each gate have four emitters. This means that NAND gates with up to four inputs can also be implemented with a different metal layer. Although no passivation layer is visible, there are no metal surfaces on the unused emitter contacts. It must be assumed that these contacts are exposed. This entails the risk of contamination entering the active area.
The HFO D100 (https://www.richis-lab.de/logic31.htm (https://www.richis-lab.de/logic31.htm)) is quite similar to this SN7400S...
(https://www.richis-lab.de/images/logic/53x07.jpg)
Texas Instruments shows a picture of the SN5400 specified for higher temperatures in a 1965 datasheet. From there to the die we have here you can see a certain evolution. The large transistors and the arrangement of the elements are very similar but not quite the same.
https://www.richis-lab.de/logic39.htm (https://www.richis-lab.de/logic39.htm)
:-/O
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Wow, never seen that red thing before. :o
The name suggests its purpose was for storage, but the wider golden strips at the sides makes it look like a socket. :-//
Is that wider golden end of each pin because that is a socket, or is it wider because the pins were not yet cut/separated from the metal frame?
Then, the shape of the red plastic looks too elaborate to be just a storage/protection package, looks like it was made to fit with something else. Was it the equivalent of today's reels/feeders for automated assembling machines?
So, what for was that Mech-Pak carrier?
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The packaging on this is not your normal garden variety package used in everyday applications. This is for special high-reliability applications like radiation hardened and space. The package is NOT cheap. In today's dollars, your normal J/N packages (the old ceramic dips you're used to) would cost under a dollar. This package would cost probably $20-30. The overall part cost for your garden variety commercial/industrial units would be cheap compared to this. Think of 2$ compared to 200$. These parts aren't sold in million piece quantities, they're ordered maybe in the hundreds at a time.
The glass insulation of the pins from the housing is to completely seal the package against any leaks of liquids or gas. Even hydrogen gas getting into the package in these environments can be very detrimental to the die. Units like this have to go through specialized leak testing before shipment to the customer.
The Mech-Pak carrier is meant to protect the pins from potentially being bent as the part is handled from assembly through test and shipping until the customer installs it on their board. It is meant to interface with the test system so that the part would not need removed from the carrier for test.
There is a reason you don't see any passivation on the die as well. Passivation usually included a PEN (plasma etched nitride) step over the normal silicon dioxide. The issue is that in radiation environments nitride will trap charge much more than the normal oxide and this would make the chip function fail at a lower radiation level.
Any other questions?
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Thanks for adding all the information. :-+
There is a reason you don't see any passivation on the die as well. Passivation usually included a PEN (plasma etched nitride) step over the normal silicon dioxide. The issue is that in radiation environments nitride will trap charge much more than the normal oxide and this would make the chip function fail at a lower radiation level.
But why didn´t they put a metal square on top of the unused emitter contacts?
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But why didn´t they put a metal square on top of the unused emitter contacts?
That's a good question I can't answer offhand. As an IC designer, my first inclination would be that ALL contacts must be covered by metal to ensure nothing can get into silicon junctions.
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(https://www.richis-lab.de/images/logic/54x01.jpg)
(https://www.richis-lab.de/images/logic/54x02.jpg)
The SN7404 contains six inverters. Like the SN7400S, the SN7404S is placed in a flat package suspended in a Mech-Pak carrier. This part was manufactured at the end of 1969.
(https://www.richis-lab.de/images/logic/54x03.jpg)
As with the SN5400 and SN7400 variants, it is important to note that the pin assignment is not always the same. “The TTL Data Book for Design Engineers - Second Edition” shows us the difference. The SN7404S contains the right-hand architecture, but is so old that it is no longer mentioned.
(https://www.richis-lab.de/images/logic/54x04.jpg)
The edge length of the die is 1,5mm. The six inverters are clearly visible. Extensive auxiliary structures can be seen in the corners. A test transistor has been integrated at the top edge.
(https://www.richis-lab.de/images/logic/19x02.jpg)
The design has been optimized a lot im comparison to the newer SN7404: https://www.richis-lab.de/logic16.htm (https://www.richis-lab.de/logic16.htm)
(https://www.richis-lab.de/images/logic/54x05.jpg)
The input transistor in the bottom left-hand corner has a large base area, which would provide space for several emitters and therefore several inputs. However, these additional emitters are missing here. The resistors offer several alternative contacts that make it possible to set the operating points of the individual stages of the inverters.
https://www.richis-lab.de/logic40.htm (https://www.richis-lab.de/logic40.htm)
:-/O
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(https://www.richis-lab.de/images/logic/55x01.jpg)
(https://www.richis-lab.de/images/logic/55x02.jpg)
One more SN74xxS. The SN7420S contains two NAND gates with four inputs each.
(https://www.richis-lab.de/images/logic/55x03.jpg)
Remember, the pinout is different than "today".
(https://www.richis-lab.de/images/logic/55x04.jpg)
The edge length of the die is 1,1 mm. The two NAND gates are clearly visible. The inputs end in the familiar large transistors with four emitter areas.
https://www.richis-lab.de/logic41.htm (https://www.richis-lab.de/logic41.htm)
:-/O
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(https://www.richis-lab.de/images/logic/56x01.jpg)
(https://www.richis-lab.de/images/logic/56x02.jpg)
SN7474S with two flip-flops in the flat package and the Mech-Pak carrier we have already seen.
(https://www.richis-lab.de/images/logic/56x03.jpg)
Be careful with the pinout!
(https://www.richis-lab.de/images/logic/56x04.jpg)
The edge length of the die is 2,0mm x 1,5mm. The flip-flops are arranged symmetrically around the center.
https://www.richis-lab.de/logic42.htm (https://www.richis-lab.de/logic42.htm)
:-/O
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Somehow you've managed to find a trove of high-rel parts somewhere! I know companies often just bin leftover units because they often have some remaining after production, but given the cost usually involved on these parts (not to mention the smaller order quantities) that's a lot more rare.
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A surprising number of these actually pop up on eBay (for example, https://www.ebay.com/itm/126980467234 (https://www.ebay.com/itm/126980467234), or search "gold flatpack IC"). My only guess for how the NOS stuck around for so long is as military spare parts for old aircraft computers, etc. where they wanted a stock of spares always on-hand at repair depots.
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I got these as a small lot from Ebay. One is left.
But I have also some more modern MIL logic here.
...and I will get a cool lot of parts that were used in the Giotto mission: https://en.wikipedia.org/wiki/Giotto_(spacecraft) (https://en.wikipedia.org/wiki/Giotto_(spacecraft)) ...of course not the parts that were on the mission. ;D
So much to do... :-/O ;D
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(https://www.richis-lab.de/images/logic/57x01.jpg)
The Harris Semiconductor CD74HCT14 contains six inverting Schmitt triggers.
(https://www.richis-lab.de/images/logic/57x02.jpg)
The edge length of the die is 1,6mm x 1,1mm. 13685A could be an internal project designation. The six Schmitt triggers are clearly visible.
This image is also available in a higher resolution: https://www.richis-lab.de/images/logic/57x02XL.jpg (https://www.richis-lab.de/images/logic/57x02XL.jpg) (22MB)
(https://www.richis-lab.de/images/logic/57x03.jpg)
The damage to the thinner wire was probably caused by the decapping. The cause of the dark artifacts on the thicker line remains unclear.
https://www.richis-lab.de/logic43.htm (https://www.richis-lab.de/logic43.htm)
:-/O
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(https://www.richis-lab.de/images/logic/57x04.jpg)
The Schmitt trigger in the bottom left-hand corner is used for a more detailed analysis.
This image is also available in a higher resolution: https://www.richis-lab.de/images/logic/57x04XL.jpg (https://www.richis-lab.de/images/logic/57x04XL.jpg) (24MB)
(https://www.richis-lab.de/images/logic/57x05.jpg)
In CD74HCT14, the NMOS transistors are located in p-doped wells. The substrate is n-doped. The frames of the NMOS wells are partially visible. In line with this, the frame structure of the die carries the Vdd potential rather than the GND potential.
(https://www.richis-lab.de/images/logic/57x06.png)
There is a protective structure at the input of the Schmitt trigger. The resistor R1 limits the current flow into the circuit. The diode D1 cuts overvoltages. This is followed by an element whose function is not self-explanatory. It appears to be an NMOS transistor that lacks the typical gate electrode. In the right-hand area, the metal layer is slightly wider and could act as a special gate electrode. MOSFETs that use the field oxide as a gate oxide are often used in protective circuits. This special feature increases the threshold voltage, making the MOSFET conductive much later and making it more suitable for overvoltage protection. The circuit itself is known as a grounded gate NMOS. Such a MOSFET becomes conductive with ESD pulses and negative voltages. The MOSFET also represents a certain resistance as it is looped into the line. This measure presumably improves the behavior with ESD pulses with large gradients. A small contact can be seen at the end of the protective structure, which is apparently another diode.
The circuit at the input of the CD74HCT14 is relatively complex as it has to represent the hysteresis of the Schmitt trigger. Two PMOS transistors are connected in series on the Vdd side. On the GND side, there are even four NMOS transistors in a series and parallel circuit. The transistors M9, M13 and M14 are controlled via the output of the stage. They intervene between the series circuits and thus form a feedback loop. This results in the desired hysteresis.
Four inverter stages are following. The areas increase steadily up to the large output stage transistors. The high number of inverter stages increases the delay of a signal, but it is necessary so that the gate electrodes of the large output stage transistors can be recharged quickly enough. The M12 transistor forms a further feedback loop around the M10/M11 inverter. The unused PMOS transistor M15 is also located in this area.
https://www.richis-lab.de/logic43.htm#schematic (https://www.richis-lab.de/logic43.htm#schematic)
:-/O
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Wow, the high-res picture looks astonishing in full screen! :o
Stare at it for too long, and now I have so many questions.
-1. Was the chip functional? Asking because the metal traces looks fractured many times, from one edge to other, particularly in the most wide traces. Are those crack-lines going deep enough into the metal layer, so to interrupt its continuity?
-2. Another thing, trying to match the die pics with typical CMOS gate structures in TI application notes. This one is about the MOSFETs area ratio: https://www.ti.com/lit/an/scla011/scla011.pdf (https://www.ti.com/lit/an/scla011/scla011.pdf)
HC vs HCT input MOSFETs area - Fig.6 from scla011 pdf - TI
(https://www.eevblog.com/forum/projects/logic-ics-die-pictures/?action=dlattach;attach=2532815;image)
The threshold voltage of a CMOS circuit is determined by the geometry of the input transistors. These transistors are designed to sink the same input current at the required threshold voltage. The resulting voltage at the output is equivalent to 50% of the supply voltage VCC . For an HC circuit, the channel width of the p-channel transistor of the input is approximately twice the value of an n-channel transistor. The purpose is to make both transistors have the same current characteristics, thus making the threshold voltage of their input at about 50% of the supply voltage VCC . This circuit area has been modified for HCT devices: the n-channel transistor is about seven times wider than the p-channel transistor (see Figure 6). This shifts the threshold voltage in a way that it amounts to 30% of the supply voltage. At a supply voltage VCC = 5 V, the threshold voltage is VT = 1.5 V, similar to the threshold voltage of TTL circuits.
The area ratio was easy to confirm for the output MOSFETs: M22 on the die (or M20 in the schematic, I guess that's a numbering typo) is indeed about twice the size of the M21 (same as the HC series would require for its input MOSFETs, because the output of HCT series has a symmetric characteristic of N vs P channel MOSFET).
Now, for the input MOSFETs of this 74HCT14, the area ratio has to be about 1:7 for P vs N channel MOSFETs, according to the same Fig.6 above. In the schematic, there is (M7+M8) for P channel, and the parallel (M2+M3) || (M4+M5). So, the area of (M7+M8) vs (M2+M3) should be about 1:3.5, did I got it right so far?
The question is: When looking at the annotated dieshot, M3 seems to be made of 2 identical structures in parallel. Is M3 (on the die) made out of 2 parallel MOSFETs? (same question for M2). Asking because my skill of identifying transistors on a die are practically zero.
-3. Another question, you say one can almost see the doping wells. How visible is that, or how to recognize the wells borders? Is it the green thing in the high res pic?
Asking because I'm trying to match the die layout with this expected layout from Figure 15 in https://www.ti.com/lit/an/scla007a/scla007a.pdf (https://www.ti.com/lit/an/scla007a/scla007a.pdf) :
(https://www.eevblog.com/forum/projects/logic-ics-die-pictures/?action=dlattach;attach=2532819;image)
One page before Fig.15 above, the TI AN describes 2 possible types of ESD protection. Would be interesting to see how much of that can be matched with this 74HCT14 die, particularly since this model is a rad-hard chip (doh, my bad, I notice now this 74HC14 is a normal DIL14, no Mech-Pak carrier). I have another set of questions about that, but this post is already too long.
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Noopy, as always, thank you for your effort! :-+
Those old Lattice chips bring back memories. Back in the mid-1990's, as a side job while still in engineering school, I helped an industrial client with the design of an arbitrary waveform generator. The device contained some interesting chips for that time, e.g. a programmable PLL, dual ported SRAM and an HDPLD.
"The global routing pool is full" is something that has been edged into my memory.
Back then, a digitally programmable PLL was interesting enough for a short oral recitation at school. An effective algorithm for automatically finding the parameters for a required waveform prepared me for setting up the clock system of STM32's. ;)
At first, I had huge problems serially programming the parameters into the PLL. While assembling the prototype, I had used DIL sockets with integrated 100nF cappas - ready for TTL power supplies. Unfortunately, what was VCC/VSS on TTL, was DataIn and ClockOut for that PLL, whose vendor/type I can't remember. Tracking down that bug was a real experience. :palm:
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Wow, the high-res picture looks astonishing in full screen! :o
I really like my microscope objectives. 8) Here I used the UMPlanFl 50x 0,80 BD.
-1. Was the chip functional? Asking because the metal traces looks fractured many times, from one edge to other, particularly in the most wide traces. Are those crack-lines going deep enough into the metal layer, so to interrupt its continuity?
I´m not 100% sure but I assume these are artefacts in the structure of the metal and not cracks. Aluminium should be ductile enough to withstand a lot of stress.
I don´t know if the chip was functional but I bought it on ebay as working.
-2. Another thing, trying to match the die pics with typical CMOS gate structures in TI application notes. This one is about the MOSFETs area ratio: https://www.ti.com/lit/an/scla011/scla011.pdf (https://www.ti.com/lit/an/scla011/scla011.pdf)
Interesting! :-+
Now, for the input MOSFETs of this 74HCT14, the area ratio has to be about 1:7 for P vs N channel MOSFETs, according to the same Fig.6 above. In the schematic, there is (M7+M8) for P channel, and the parallel (M2+M3) || (M4+M5). So, the area of (M7+M8) vs (M2+M3) should be about 1:3.5, did I got it right so far?
Yes, should be right.
The question is: When looking at the annotated dieshot, M3 seems to be made of 2 identical structures in parallel. Is M3 (on the die) made out of 2 parallel MOSFETs? (same question for M2). Asking because my skill of identifying transistors on a die are practically zero.
You could say that in M2 there are four MOSFETs. Every greenish gate electrode is one MOSFET. Left an right of the gate is drain and source and the MOSFETs are sharing them.
-3. Another question, you say one can almost see the doping wells. How visible is that, or how to recognize the wells borders? Is it the green thing in the high res pic?
Asking because I'm trying to match the die layout with this expected layout from Figure 15 in https://www.ti.com/lit/an/scla007a/scla007a.pdf (https://www.ti.com/lit/an/scla007a/scla007a.pdf) :
(https://www.eevblog.com/forum/projects/logic-ics-die-pictures/?action=dlattach;attach=2532819;image)
In the TI picture you see two wells in the CD74HCT14 you have just a well for the NMOS like you can see it here:
https://toshiba.semicon-storage.com/eu/semiconductor/knowledge/e-learning/cmos-logic-basics/chap2/chap2-4.html (https://toshiba.semicon-storage.com/eu/semiconductor/knowledge/e-learning/cmos-logic-basics/chap2/chap2-4.html)
Look at M3 on the left side, left of the metal trace you can see the edge of the well. As soon as you have recognised this edge you can find more of them. But you can´t see every well edge and of course just at the NMOS transistors.
One page before Fig.15 above, the TI AN describes 2 possible types of ESD protection. Would be interesting to see how much of that can be matched with this 74HCT14 die, particularly since this model is a rad-hard chip (doh, my bad, I notice now this 74HC14 is a normal DIL14, no Mech-Pak carrier). I have another set of questions about that, but this post is already too long.
The ESD protection TI shows is similar but not the same. At least I assume that this is the case. The grounded gate NMOS does not work like a normal MOSFET. When there is an ESD pulse a parasitic bipolar transistor in its structures becomes conductive. The TI circuit adds a latching structure so it stays conductive. In my view the the structures in the 74HCT14 are to simple for such a latching circuit.
Now feel free to go on with the circuit analysis. ;D
Noopy, as always, thank you for your effort! :-+
It´s a pleassure! :)
Those old Lattice chips bring back memories. Back in the mid-1990's, as a side job while still in engineering school, I helped an industrial client with the design of an arbitrary waveform generator. The device contained some interesting chips for that time, e.g. a programmable PLL, dual ported SRAM and an HDPLD.
"The global routing pool is full" is something that has been edged into my memory.
Back then, a digitally programmable PLL was interesting enough for a short oral recitation at school. An effective algorithm for automatically finding the parameters for a required waveform prepared me for setting up the clock system of STM32's. ;)
At first, I had huge problems serially programming the parameters into the PLL. While assembling the prototype, I had used DIL sockets with integrated 100nF cappas - ready for TTL power supplies. Unfortunately, what was VCC/VSS on TTL, was DataIn and ClockOut for that PLL, whose vendor/type I can't remember. Tracking down that bug was a real experience. :palm:
Sounds interesting and very educational. ;D :-+
EDIT: I corrected the M20/M22 typo. Thanks! :-+
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(https://www.richis-lab.de/images/logic/58x01.jpg)
SNJ54S38, the Schottky-Variante des 5438 and of course the MIL variant. 8)
(https://www.richis-lab.de/images/logic/58x02.jpg)
(https://www.richis-lab.de/images/logic/58x03.jpg)
The dimensions of the die are 1,2mm x 1,1mm. Texas Instruments usually integrates a Ti logo. Here there is no such logo. The character sequence S38 refers to the 54S38 variant. As will be shown shortly, another variant can also be build on this die. The letter A could stand for a first revision.
(https://www.richis-lab.de/images/logic/58x04.jpg)
The structures are still quite clear.
(https://www.richis-lab.de/images/logic/58x07.jpg)
The base contacts of the transistors contact both the base and collector areas. A Schottky contact is created between the metal layer and the weaker n-doping of the collector, which makes the transistor a Schottky transistor. Such a transistor does not saturate and can therefore be switched off more quickly.
(https://www.richis-lab.de/images/logic/58x05.jpg)
The individual elements of the circuit can be easily identified.
(https://www.richis-lab.de/images/logic/58x06.jpg)
Three transistors and three resistors are not included in the circuit. These additional components can be used as an alternative to the 54S00. The 54S00 also contains four NAND gates, each with two inputs, but has a push-pull output.
It is noticeable that the resistance values in the datasheets of the 54S38 and the 54S00 are significantly different. This may be due to the fact that the datasheets describe different generations. If the specifications of the transistors change when switching to a different process, the resistors must also be adjusted. In addition, the exact resistance values are hardly relevant for the user and are subject to large tolerances. Accordingly, the datasheets indicate that these are only nominal values.
https://www.richis-lab.de/logic44.htm (https://www.richis-lab.de/logic44.htm)
:-/O
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(https://www.richis-lab.de/images/logic/58x08.jpg)
A minor correction:
The 54S38 contains four NAND gates with two inputs each and powerfull open collector outputs (they are buffers).
Because of that the related 54 variant is not the 54S00 (weak output) but the 54S37 (buffer output)!
Now the resistor values are more similar too. ;D
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(https://www.richis-lab.de/images/logic/59x01.jpg)
The National Semiconductor DM74LS14 contains six inverting Schmitt triggers.
(https://www.richis-lab.de/images/logic/59x02.jpg)
(https://www.richis-lab.de/images/logic/59x03.jpg)
The assembly technology is surprising. No bondwires were used. The die was contacted directly via a small punched grid. This small grid is connected halfway with a larger punched grid, which ultimately forms the pins. The surface structures of the epoxy material suggest that the package was built in two steps. The two-part punched grid would fit in with this.
(https://www.richis-lab.de/images/logic/59x04.jpg)
The edge length of the die is 1,3mm x 1,1mm. The character sequence 54LSR14 is shown in the bottom right-hand corner. How the R is to be assigned remains open. The revisions of five masks are shown in the top right-hand corner. The six Schmitt triggers are not immediately recognizable, but can still be easily distinguished.
(https://www.richis-lab.de/images/logic/59x06.jpg)
That´s a ... ... ... silicon art, a face!?
(https://www.richis-lab.de/images/logic/59x05.jpg)
The circuit is still quite simple.
https://www.richis-lab.de/logic45.htm (https://www.richis-lab.de/logic45.htm)
:-/O
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(https://www.richis-lab.de/images/logic/60x01.jpg)
(https://www.richis-lab.de/images/logic/60x03.jpg)
Another MIL-STD-883 SN54JAS04 logic. Here we have the "Advanced Schottky" with two AND gates with four inputs each.
(https://www.richis-lab.de/images/logic/60x02.jpg)
(https://www.richis-lab.de/images/logic/60x04.jpg)
The dimensions of the die are 1,3mm x 1,4mm. As usual for Texas Instruments, the Ti logo is shown in the bottom left-hand corner. A test structure is integrated in the bottom right-hand corner. This is not an active element. Apparently, the three contacts can only be used to measure a homogeneous surface.
(https://www.richis-lab.de/images/logic/60x06.jpg)
There are quite efficient test structures on the bottom and right edges of the die, which allow the alignment of the masks to be determined relatively easily and accurately. As with a sliding gauge, the distances between the small strips in the different layers are different, so that the degree of displacement is very clear. Bottom an left is for X and Y shift.
(https://www.richis-lab.de/images/logic/60x05.jpg)
The character sequence 54AS00 is shown in the substrate in the top left-hand corner of the die. Below this, the metal layer shows the character sequence 54AS21. This suggests that the design can represent several variants of the 54/74 logic. The structure of the circuit matches this. It is clearly visible that the die contains the same circuit four times. Apart from the input transistors, only the right-hand circuit is used in each case.
It is very likely that the design can display at least the SN54AS00 (4*2-input NAND), the SN54AS08 (4*2-input AND) and the SN54AS20 (2*4-input NAND) in addition to the SN54AS21 (2*4-input AND). While the left-hand side only has two input circuits, three input circuits are integrated on the right-hand side. It is therefore conceivable that the logic variants with three inputs can also be displayed on this design (SN54AS10 and SN54AS11). A third gate must then be constructed from the parts on the left side.
https://www.richis-lab.de/logic46.htm (https://www.richis-lab.de/logic46.htm)
:-/O
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Still working on getting that PT2399 cleanly decapped, but meanwhile, here's a logic chip to look at...
I scored an interesting module on Xianyu recently, which looks like it was part of a Chinese radio (aviation? military?). The components and construction are a strange mix of Soviet-era Russia, USA/western-Europe, and uniquely Chinese. Fascinating comparing the sourcing of different pieces. Anyways, it has a row of these ICs, and as there's no way I'm going to find any data on them, I need to open them up to figure out what they do, so that I can reverse-engineer the circuitry in the module.
(https://live.staticflickr.com/65535/54474547427_5db1f046d7_c.jpg)
Luckily, most of them are the same model: this "T076BA DG II", except for one that I'll be looking at in the future.
Here's the die:
(https://live.staticflickr.com/65535/54475388996_7aa76ea896_b.jpg)
- It looks like TTL: there's clearly sets of nested wells which scream "bipolar transistor" to me, and not much in the way of resistors
- Ground was easy to find because it connects to the substrate in a couple places, and that pin connects externally to the enclosure/shield
- There's a protection diode on each input pin, which made it easier to figure out which silicon doping was which: I used my multimeter's diode check to check the polarity of these diodes relative to ground, which told me that the substrate was P-type and the 1st (outer) wells were N-type. From here, it was easy to look at the alternating nested wells, and figure out that the transistors were all NPNs, and where the base connections were.
- The "T076" marking is reversed: that's not an artifact of my microscope setup. Someone didn't account for the various flips when making the mask?
Here's the contents, labeled:
[attachimg=1]
When traced, it results in this transistor-level schematic:
[attachimg=2]
At first, I was very confused about which side was the collector and which was the emitter, on each transistor, because of the connections of Q1-Q15, Q2-Q14, etc.
I'm not too familiar with IC design or TTL circuit details, so the workings may be obvious to others here, but I spent a lot of time trying to figure out what I'd done wrong despite the very simple connections & process. I couldn't figure out where the base current to Q12-15 was coming from. It turns out that the designers get their full usage out of every PN junction, though, by selectively forward-biasing the base-collector junctions of the multi-emitter transistors. Q1-4 are used more like diode arrays than a traditional current-amplifier role.
Let's look at Q1 and Q15, for example: when all the Q1 emitters are high, the transistor is off. Base current flows through R1, then the base-collector diode, and into Q15's base. The common connection with Q10 sets the Q1 collector voltage to 2*Vbe above ground, so that this next part can work correctly. When any of the Q1 emitters is brought low (below the Q1 collector voltage), it now forward-biases the base-emitter junction, turns on Q1, and "steals" the Q1 base current. Now, the base-collector junction is no longer forward-biased, so Q15 turns off.
The same is done with Q9/Q6 & Q5/Q11: Q5 & Q9 get their base current through Q6 & Q11's forward-biased base-collector junctions, when the Q6 & Q11 emitters are high.
The right-most sections are obviously power stages to drive the output pins. Q18 & Q19 are Darlington arrangements, with both transistors living in the same collector well. These provide the high-side drive, while Q16 & Q17 provide the low-side drive. R7 & R8 provide base current to the high-side Darlingtons, until Q8 or Q7 turns on and shunts this current to the bases of the low-side drivers instead.
Q20 & Q21 have a strange arrangement which I don't completely understand, and might use the lateral resistance of the base somehow? They seem to be meant to limit the base current to the low-side drivers, maybe to keep them out of saturation (or limit the saturation).
Anyways, tracing out the equivalent logic implemented by these transistors, we end up with this:
[attachimg=3]
You can see 3 separate R-S latches made out of NAND gates. The two left-hand ones are cross-coupled to each other, as well.
The connections are easy, but figuring out the intent behind the 3-way-coupled latches seemed much more difficult, so I looked at common logic-gate implementations of standard flip-flop types: it looked like it would be a J-K or D flip-flop. Turns out, the D-flip-flop diagram shown on Wikipedia matches perfectly: https://en.wikipedia.org/wiki/File:Edge_triggered_D_flip_flop_with_set_and_reset.svg (https://en.wikipedia.org/wiki/File:Edge_triggered_D_flip_flop_with_set_and_reset.svg)
Matching it up with the gate-level schematic above:
Pin 10 is ~Reset
Pin 13 is Clock
Pin 4 is ~Set
Pins 1, 2, and 3 are Data: all effectively AND'ed together?
Pins 5 & 9 don't have a direct equivalent: it looks like pins 4 & 10 are a synchronous Set/Reset while pins 5 & 9 are asynchronous Set/Reset?
Now knowing that all these chips are D-flip-flops, and having their pinout of these chips, it shouldn't be hard to figure out what this module is doing (probably a frequency divider)...once I decap and trace the other unique IC onboard. Hope this was interesting.
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The components and construction are a strange mix of Soviet-era Russia, USA/western-Europe, and uniquely Chinese.
The who and why behind such constructions would be interesting.
Today we have everything we need it´s just a matter of how much money you want to spent. Back in the days in the eastern bloc the engineers had to do the job with the things they had around. :-/O
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Very true!
Here's the other unique IC in that same module: marked T068.
(https://live.staticflickr.com/65535/54485553159_098d7c0d57_c.jpg)
This one's much simpler:
[attachimg=1]
Mapping out the circuitry, we can see that it has 2x 4-input NAND gates.
[attachimg=2]
The behavior of the multi-emitter input transistors, and the output stages, is identical to the circuitry in the T076 I described in the previous post.
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Hijacking the thread to include thick film hybrids, Burr-Brown once produced a calendar with the images shown at https://entertaininghacks.wordpress.com/2015/07/07/images-of-late-70s-burr-brown-thick-film-hybrid-ics/
Since it was a "coo-ee look at the pretty pictures" exercise, they didn't bother to give any information about the devices :(
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Here's the other unique IC in that same module: marked T068.
(https://live.staticflickr.com/65535/54485553159_098d7c0d57_c.jpg)
In the lower area the surface looks really ugly! ;D
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Yes! Meant to point that out, it looks like something went wrong with the process there?
Hijacking the thread to include thick film hybrids, Burr-Brown once produced a calendar with the images shown at https://entertaininghacks.wordpress.com/2015/07/07/images-of-late-70s-burr-brown-thick-film-hybrid-ics/
Yeah those are great, stumbled on that a few years back and that's part of what started me eventually on opening up hybrids to look at the insides. Wish there were part numbers.
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Yes! Meant to point that out, it looks like something went wrong with the process there?
Perhaps there went something wrong. But it´s also possible that the process just was this bad. ;D
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(https://www.richis-lab.de/images/logic/61x01.jpg)
(https://www.richis-lab.de/images/logic/61x02.jpg)
The SN74121S contains a monoflop. It is one more flat package suspended in a Mech-Pak carrier. 8)
(https://www.richis-lab.de/images/logic/61x03.jpg)
In addition to the SN74121, there is also a SN74L121, in which the integrated charging resistor has twice the resistance. This resistor can be used to set the duration of the output pulses.
(https://www.richis-lab.de/images/logic/61x04.jpg)
The edge length of the die is 1,3 mm x 1,5 mm. Extensive auxiliary structures are integrated in the corners, which make it possible to monitor the alignment of the masks and the quality of the process steps.
(https://www.richis-lab.de/images/logic/61x05.jpg)
At the upper edge you can find the charging resistor, which has twice the resistance value in the SN74L121. The loop is obviously extended for this purpose. The gray n-doped area offers corresponding free space. The variation in resistor length is unusual. Usually a large resistor with a center tap is created and two different masks are used for the metal layer.
https://www.richis-lab.de/logic47.htm (https://www.richis-lab.de/logic47.htm)
:-/O
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Hm, I'm not sure about how they changed the resistor value. Some of the other specifications are different for the L variant too. Someone had the theory that they changed the doping levels. :-//
I will have to clarify this... Unfortunately these old logic parts are hard to get...
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Hm, I'm not sure about how they changed the resistor value. Some of the other specifications are different for the L variant too. Someone had the theory that they changed the doping levels. :-//
I will have to clarify this... Unfortunately these old logic parts are hard to get...
I wouldn't think doping levels would be changed considering this looks to be the old seven-layer bipolar process. Changing the doping would make huge differences in transistor performance, breakdown voltages, etc. and isn't something that would be easy to do.
I see a number of places where resistor sizes can be adjusted. Considering that this would be swapping one mask for a different one, it would be the same as having a different metal mask. Just a different point in the process where you change masks.
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I´m skepticle too. It would be very odd to change the doping of a process to get twice the resistance of the base layer. Nevertheless the other values are different too. That´s also strange. I will get a 54L121 soon. I hope it´s the same revision.
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(https://www.richis-lab.de/images/logic/62x01.jpg)
The RCA CD4035 contains a four-stage shift register. This is the CD4035BK variant. Shift registers with the index B offer a voltage resistance of 20V, while the index A only allows 15V. The index K stands for the so-called flat package.
The component was put in a very special transport package. A note is printed on the package indicating that this is a MOS component that can be damaged very quickly by electrical discharges. Two cutouts allow a view of the top and bottom of the CD4035.
(https://www.richis-lab.de/images/logic/62x02.jpg)
(https://www.richis-lab.de/images/logic/62x03.jpg)
The transport package is made of cardboard. A plastic clip ensures that the IC does not get lost. The inside of the transport package is lined with aluminum foil. All pins are short-circuited, which prevents the build up of problematic voltages.
(https://www.richis-lab.de/images/logic/62x04.jpg)
The datasheet contains a block diagram of the CD4035. The four shift registers can be written to and read from serially and in parallel.
(https://www.richis-lab.de/images/logic/62x06.jpg)
The dimensions of the die are 2,3 mm x 2,2 mm. The numbers 10165 on the upper edge could be an internal project designation. There are also various auxiliary and test structures on the edges.
This image is also available in a higher resolution: https://www.richis-lab.de/images/logic/62x06XL.jpg (https://www.richis-lab.de/images/logic/62x06XL.jpg) (7MB)
(https://www.richis-lab.de/images/logic/62x05.jpg)
The datasheet contains an image of the metal layer. This image corresponds to the structures on the die.
https://www.richis-lab.de/logic48.htm (https://www.richis-lab.de/logic48.htm)
:-/O
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These are cool.
Have you ever done any of the 4046 series ?
eg HEF4046 / CD4046 / 74HC4046 / 74LV4046 and side variants now less common/eol like 74HC7046, 74HC9046
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Thanks!
Sorry, up to now I don´t have a 4046 in the queue. But I can keep my eyes open... :-/O
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Is it only me, or are the SSI and MSI devices far more beautiful to look at than LSI or VLSI ones?
At least for me, the feature size in SSI and to some extent MSI, are large enough to be easily distinguishable in an image that displays the complete die.
For VLSI, an image that displays the complete die, one can only distinguish different-colored areas and patterns. Not the intricate and beautiful artwork of the components and interconnections themselves.
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I totally agree with you.
There is also a "photographic problem" with these huge, highly integrated circuits. I know people taking technically perfect pictures with the maximum possible details. Unfortunately these pictures are huge. It's no fun to trace lines (if it is even possible) and it's often hard to even open and modify the pictures.
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(https://www.richis-lab.de/images/logic/63x01.jpg)
We have talked about the SN74121S. Now let´s take a look into a SN54L121. We have focused on the bigger charching resistor of the L variant but we have to clarify: The L indicates that this is the “low power” version. It is slightly slower, but also offers significantly lower power consumption. Texas Instruments specifies a reduction by a factor of 10 for a single gate.
(https://www.richis-lab.de/images/logic/63x02.jpg)
The die largely corresponds to the die in the SN74121S. It appears to be merely a different revision. The number sequence 121 is shown in the metal layer. The numbers 21 are integrated in the base mask. Only the geometry of one transistor has been minimally changed. All other functional structures are identical to those of the SN74121S. The load resistor in the L variant is also geometrically the same size. This means that at least the doping of the base layer differs significantly between the two variants. Apparently, Texas Instruments only had to adjust the process parameters during manufacturing to produce the low-power variants.
(https://www.richis-lab.de/images/logic/63x03.jpg)
The metal layer is damaged at one point. Since the electrical connection is still intact, the component was most likely still functional. However, such a defect can lead to failure in extreme conditions or over longer periods of operation.
https://www.richis-lab.de/logic49.htm (https://www.richis-lab.de/logic49.htm)
:-/O
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(https://www.richis-lab.de/images/logic/64x01.jpg)
The U106, produced in the "Funkwerk Erfurt", contains four NOR gates, each with two inputs. The circuit is based on p-channel MOSFETs. It is similar to the MEM1013 from General Instruments. This U106 was produced in the second quarter of 1979. The Romanian semiconductor manufacturer Microelectronica produced these NOR gates under the designation MMP106.
(https://www.richis-lab.de/images/logic/64x06.jpg)
According to General Instruments, the so-called MTOS process was used for the MEM1013 family. In the March 1967 issue of Electronic Design magazine, General Instruments describes this MTOS process in more detail. Usually, a silicon oxide that is as thin as possible is applied under the gate electrode of a MOSFET. This ensures that the gate potential has the greatest possible influence on the conductive channel below it. However, as shown on the left, even small disturbances can lead to short circuits. General Instruments advertises that, as part of the MTOS process, it uses a gate oxide that is just as thick as the so-called field oxide found on the remaining surfaces of the semiconductor. This enables them to achieve a higher yield and offer lower unit prices. It seems that it has been accepted that this measure impairs the electrical properties of the transistors.
(https://www.richis-lab.de/images/logic/64x02.jpg)
In 1971, the Funkwerk Erfurt presented the first MOS circuits based on the MEM1000 series at the Leipzig Spring Fair. These included the U101 with two full adders, the U102 with two NOR gates, the U103 with two RS flip-flops, the U104 with antivalence equivalence gates, and the U105 with six simple switches. Other variants such as the U106 followed later.
(https://www.richis-lab.de/images/logic/64x03.jpg)
When you open the package, you can see that the die has been additionally protected with a soft potting.
(https://www.richis-lab.de/images/logic/64x04.jpg)
The dimensions of the die are 1,3mm x 1,4mm. No passivation layer was applied. Therefore, scratches occur in the metal layer when the potting material is removed.
(https://www.richis-lab.de/images/logic/64x07.jpg)
On closer inspection, it can be seen that the more common MOS transistors with a thin gate oxide have been integrated. Corresponding frames are visible in the surface structure of the electrodes. Consequently, only the circuitry of the MEM1013 has been replicated, but not the MTOS technology.
Two test structures have been set up on one edge. The one on the left is a MOSFET. The one on the right is missing the frame in the area of the gate electrode. This made it possible to check the influence of the metal layer in places where no transistor is to be formed and where a conductor bridges two p-doped areas solely for the purpose of potential conduction.
Above the test structure, the revisions of four masks are shown, which have apparently been revised several times. Below, the squares allow the alignment of the masks with each other to be evaluated.
(https://www.richis-lab.de/images/logic/64x05.jpg)
Like the MEM1013, the U106 operates with two supply voltages. A voltage of -27V must be applied between U1 and ground. The chip expects a voltage of -13V between U2 and ground. The second ground potential in the upper right corner does not match the distribution of potentials on the pins of the package. There, the second ground potential is located between e41 and e32. It could be that the bondpad in the upper right corner is connected to the metal grid under the die and that the pin between e41 and e32 also contacts this metal grid.
(https://www.richis-lab.de/images/logic/64x08.jpg)
Protective structures are located between the supply potentials and the ground potential, which appear to represent only a certain capacity (red). Capacities have also been integrated at the inputs (yellow). The p-doped lines, together with the substrate, also act as a protective diode against excessive voltages.
(https://www.richis-lab.de/images/logic/64x09.jpg)
(https://www.richis-lab.de/images/logic/64x10.jpg)
(https://www.richis-lab.de/images/logic/64x11.jpg)
At first glance, the structures appear confusing, but the circuit is actually relatively simple. The two inputs each lead to two MOSFETs (M5/M6 and M1/M2), which can switch the ground potential. One of the MOSFETs (M5 and M1) leads directly to the output, so that a low level at one of the inputs directly generates a high level at the output.
Transistor M4 generates a low level at the output as long as none of the input transistors M6/M2 is active and raises its gate to ground potential. This part of the circuit therefore ensures that the output is low as long as both inputs are high. M3 acts as a pull-down resistor. It requires the lower supply potential U1 to be able to switch M4 on cleanly.
https://www.richis-lab.de/logic50.htm (https://www.richis-lab.de/logic50.htm)
:-/O
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(https://www.richis-lab.de/images/logic/65x01.jpg)
The U102 shown here bears the abbreviation ND, meaning it was manufactured in the fourth quarter of 1981. The U102 contains two NOR gates, each with three inputs. As described in the context of the U106, these p-MOS logic devices are based on the MEM1000 series from General Instruments. The U102 corresponds to the MEM1002.
(https://www.richis-lab.de/images/logic/65x03.jpg)
(https://www.richis-lab.de/images/logic/65x02.jpg)
The edge length of the die is 1,1 mm. It appears that the process and design specifications have been revised. While the U106 did not yet have a passivation layer, the passivation layer can be seen here through the cutouts at the bondpads. Another indication is the robustness of the metal layer. In the U106, these are heavily scratched. There is no damage visible on the U102. The mask revisions have been moved to the scribe line, so no additional silicon area is required for this. The masks have been revised up to four times.
(https://www.richis-lab.de/images/logic/65x04.jpg)
A test structure is integrated on both the right and left edges. As with the U106, one of these is a MOSFET. This MOSFET can be seen here. The left structure also consists of two p-doped areas, between which a gate electrode is applied. However, the gate electrode is not located on a thin gate oxide, but on a thick field oxide. In this design, the influence of the potential on the structures in the silicon should be as low as possible.
(https://www.richis-lab.de/images/logic/65x05.jpg)
(https://www.richis-lab.de/images/logic/65x06.jpg)
(https://www.richis-lab.de/images/logic/65x07.jpg)
The structures of the U102 are somewhat denser and therefore also somewhat less transparent than the structures of the U106. The protective structures at the inputs and between the supply potentials are the same. The circuitry of the U102 is very similar to that of the U106. However, an additional supply potential has been omitted here. Apparently, transistor M3 can sufficiently control transistor M4 even without this potential. The dynamic characteristics of the two components differ only minimally.
https://www.richis-lab.de/logic51.htm (https://www.richis-lab.de/logic51.htm)
:-/O
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A "condensed catalogue" of the MTOS devices (1967, 9.8MB pdf):
http://www.bitsavers.org/components/gi/_dataBooks/GI_MTOS_Circuit_Digest_1967.pdf (http://www.bitsavers.org/components/gi/_dataBooks/GI_MTOS_Circuit_Digest_1967.pdf)
Any idea where these chips were used??
OK AI told me (not much findings, indeed):
#1: NASA/space-instrument electronics (1969)
A NASA instrument “commutator driver” used two General Instrument MEM-3012-SP shift-register ICs cascaded to generate timing for a 20-switch commutator (explicitly named in the hardware description).
NASA Technical Reports Server
#2: Another NASA circuit report (1969)
A separate NASA technical report specifies the shift register as a General Instrument MEM-3012-SP MOS I.C., used in timing/logic for sampling (“microsecond sample window pulses”).
NASA Technical Reports Server
#3: Photographic flash system with automatic light cutoff (U.S. patent)
The patent text names GI MEM-3012-SP as the register and GI MEM-2009 as the multiplexer in the reference implementation of the flash control logic.
Google Patents
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Any idea where these chips were used??
If you're looking for the whole General Instrument series, I recently found some MEM2009 analog muxes inside a telemetry encoder (https://www.eevblog.com/forum/projects/avionics-reverse-engineering-60s-hughes-telemetry-unit/msg6016397/#msg6016397).
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(https://www.richis-lab.de/images/logic/64x06.jpg)
I have to correct myself:
With this MTOS technology General Instruments kept the gate oxide as thin as you have it with “normal” MOS transistors. They only made the oxide over undercuts thicker!
I wonder if that really made a noticeable difference...
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(https://www.richis-lab.de/images/logic/66x01.jpg)
Here you can see the circuit board of the Robotron A5105 educational computer developed in the GDR. On the left is the processor, in this case a Z80. In the GDR, they had developed their own variant of the Z80, the U880. The two UV-EPROM which are usually below the Z80 are missing. In the lower part of the PCB two square packages catch the eye. These are two ASICs based on the U1520 standard cell design system. The U1525FC007 (https://www.richis-lab.de/logic27.htm (https://www.richis-lab.de/logic27.htm)) has already been documented in detail. The second component is designated U1525FC008. This is the VIS, the video interface circuit. The free socket on the right normally houses the graphics processor. In the GDR, the U82720 (https://www.richis-lab.de/GraKa04.htm (https://www.richis-lab.de/GraKa04.htm)), a replica of the µPD7720 (https://www.richis-lab.de/GraKa02.htm (https://www.richis-lab.de/GraKa02.htm)), was used for this purpose. The U1525FC008 works closely with this graphics processor. While the graphics processor performs more complex calculations, for example to generate circles, the VIS takes care of more basic image output functions.
(https://www.richis-lab.de/images/logic/66x02.jpg)
Let's take a closer look at the U1525FC008, the video interface circuit. X9 indicates that it was manufactured in September 1989.
(https://www.richis-lab.de/images/logic/66x03.jpg)
The repair manual for the Robotron A5105 contains a block diagram that provides insight into the functions of the U1525FC008.
(https://www.richis-lab.de/images/logic/66x04.jpg)
The U1525FC008 is based on the standard cell design system U1520. More detailed information about this system and details of the circuit components can be found in the analysis of the U1525FC007 (https://www.richis-lab.de/logic27.htm (https://www.richis-lab.de/logic27.htm)).
This image is also available in a higher resolution: https://www.richis-lab.de/images/logic/66x04XL.jpg (https://www.richis-lab.de/images/logic/66x04XL.jpg) (95MB)
(https://www.richis-lab.de/images/logic/66x08.jpg)
There are three interesting artifacts on the die, two of which can be seen in this section. The most obvious is a relatively long line that at first glance resembles a hair or fiber. There is also a spot just before the interface at the upper edge.
(https://www.richis-lab.de/images/logic/66x05.jpg)
The spot is located in the polysilicon layer. It is a large round area of polysilicon. The clean edges suggest that the mask was defective at this point. Since there are no other structures in this area of the polysilicon layer, the artifact has no effect on functionality.
(https://www.richis-lab.de/images/logic/66x06.jpg)
(https://www.richis-lab.de/images/logic/66x07.jpg)
The “line” is apparently located below the functional structures in the substrate.
(https://www.richis-lab.de/images/logic/66x09.jpg)
Here, it is helpful to look at a single image without the usual focus stacking. It can be seen that the left-hand area is noticeably deeper than the right-hand area. While the metal layer is sharply focused on the left, the polysilicon layer beneath the metal layer is in focus on the right. For the UMPlanFl 50x 0.80 BD objective used for this picture the depth of field is specified as 1,3 µm. The edge must therefore be higher than 1 µm.
The U1525FC008 attracted attention because, among other things, the cursor was only displayed sporadically. This could be related to this artifact. The so-called cursor input A17 leads directly to the narrow inverter, whose input is located above the edge. According to the depth of field, the edge is highest in this area. The metal layer covers the polysilicon strip. It seems likely that the electrical connection is borderline.
(https://www.richis-lab.de/images/logic/66x11.jpg)
A little bit lower on the die is a third artifact.
(https://www.richis-lab.de/images/logic/66x10.jpg)
This disturbance looks different from the previous one. However, it is also an edge. The difference in height is less pronounced, though.
https://www.richis-lab.de/logic52.htm (https://www.richis-lab.de/logic52.htm)
:-/O
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There are three interesting artifacts on the die, two of which can be seen in this section. The most obvious is a relatively long line that at first glance resembles a hair or fiber. There is also a spot just before the interface at the upper edge.
The spot is located in the polysilicon layer. It is a large round area of polysilicon. The clean edges suggest that the mask was defective at this point. Since there are no other structures in this area of the polysilicon layer, the artifact has no effect on functionality.
The “line” is apparently located below the functional structures in the substrate.
Here, it is helpful to look at a single image without the usual focus stacking. It can be seen that the left-hand area is noticeably deeper than the right-hand area. While the metal layer is sharply focused on the left, the polysilicon layer beneath the metal layer is in focus on the right. For the UMPlanFl 50x 0.80 BD objective used for this picture the depth of field is specified as 1,3 µm. The edge must therefore be higher than 1 µm.
The U1525FC008 attracted attention because, among other things, the cursor was only displayed sporadically. This could be related to this artifact.
Looks like a full on crack/fracture in the die to me - amazing it limps along at all !
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Looks like a full on crack/fracture in the die to me - amazing it limps along at all !
I agree with you.
It´s amazing such a crack can occur inside the lattice structure. For the circuit it is huge but regarding the whole wafer it is just a minor area.
This artefact reminded me of the U840 wafer:
(https://www.richis-lab.de/images/wafer/08x03.jpg)
(https://www.richis-lab.de/images/wafer/08x04.jpg)
(https://www.richis-lab.de/wafer09.htm (https://www.richis-lab.de/wafer09.htm))
But there the damage is more noticable and it doesn´t really look like a crack. :-//
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There are three interesting artifacts on the die, two of which can be seen in this section. The most obvious is a relatively long line that at first glance resembles a hair or fiber. There is also a spot just before the interface at the upper edge.
The spot is located in the polysilicon layer. It is a large round area of polysilicon. The clean edges suggest that the mask was defective at this point. Since there are no other structures in this area of the polysilicon layer, the artifact has no effect on functionality.
The “line” is apparently located below the functional structures in the substrate.
Here, it is helpful to look at a single image without the usual focus stacking. It can be seen that the left-hand area is noticeably deeper than the right-hand area. While the metal layer is sharply focused on the left, the polysilicon layer beneath the metal layer is in focus on the right. For the UMPlanFl 50x 0.80 BD objective used for this picture the depth of field is specified as 1,3 µm. The edge must therefore be higher than 1 µm.
The U1525FC008 attracted attention because, among other things, the cursor was only displayed sporadically. This could be related to this artifact.
Looks like a full on crack/fracture in the die to me - amazing it limps along at all !
If the crack has not propagated up into the actual junctions, then it's no surprise that the circuit works. I will say that depending on the grade of product being purchased, the defects seen here should not make it through. The cheapest, most basic commercial grade chips will be processed, maybe have a cursory wafer probe to check functionality, and then assembled into packages and run through final testing without a second thought. Higher grade products will often have optical inspections done and something like this would fail immediately.
I will say that quality checks have improved greatly in the decades that I have been in the semiconductor industry, so the fact this came from 1989 may be a factor.
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I will say that quality checks have improved greatly in the decades that I have been in the semiconductor industry, so the fact this came from 1989 may be a factor.
And we have to keep in mind that the GDR always struggeld to keep up with the rest of the world.
They were always a little bit behind (still a big achievement for the small isolated GDR). The circuits were usually not as cheap as they should be. It was important to get a yield as high as possible. They also had the "Bastlertypen", the parts that didn´t fullfill the specifications but could be bought by hobbyist.
With all this in mind they probably sold a lot of parts which today would get scrapped. In the worst case they would have to change the part in the application. That was probably cheaper than loosing such a big part.
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(https://www.richis-lab.de/images/logic/67x01.jpg)
The SN7413 contains two NAND gates, each with four inputs. Unlike the SN7400, the SN7413 also has Schmitt trigger functionality at the inputs. The switching thresholds therefore differ for rising and falling input signals.
(https://www.richis-lab.de/images/logic/67x04.jpg)
The SN7413 datasheet shows the circuit, which is somewhat more complicated than the SN7400S circuit. Here, the inputs are simply connected with diodes. The two transistors that follow represent the Schmitt trigger functionality. If the potential at an input drops and the base current of the first transistor is thereby diverted, less current flows through this transistor. This allows more current to flow through the base of the second transistor. At the same time, the potential at the emitter of the second transistor is reduced because the first transistor now also allows less current to flow through the common emitter resistor. The lower emitter potential allows even more current to flow through the second transistor. This positive feedback amplifies the switching action, resulting in the desired effect of a Schmitt trigger.
(https://www.richis-lab.de/images/logic/67x02.jpg)
The dimensions of the die are 1,27mm x 1,14mm. The number 13 is shown on the right edge, corresponding to the type designation SN7413. Each corner has clearly identifiable reference marks that indicate the alignment of the masks.
(https://www.richis-lab.de/images/logic/67x03.jpg)
The circuit is easy to recognize. It corresponds to the circuit diagram in the datasheet. The two gates are arranged axially symmetrically. Only the second substrate connection in the left-hand area causes a certain degree of asymmetry. The conspicuous input transistor with four emitters is still used to combine the four input signals. Here, only the base and collector are short-circuited.
https://www.richis-lab.de/logic53.htm (https://www.richis-lab.de/logic53.htm)
:-/O
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(https://www.richis-lab.de/images/logic/68x01.jpg)
The D113 contains two NAND gates, each with four inputs. The gates offer Schmitt trigger functionality. The component is therefore equivalent to the SN7413. It is striking that there is no datasheet for the D113. It is also not mentioned in the literature. The manufacturer is the Halbleiterwerk Frankfurt Oder. LP stands for a production in September 1975.
(https://www.richis-lab.de/images/logic/68x02.jpg)
The edge length of the die is 1,20 mm. This makes it approximately the same size as the die in the Texas Instruments SN7413.
(https://www.richis-lab.de/images/logic/68x03.jpg)
A direct comparison with the Texas Instruments SN7413 reveals a very close similarity. Apart from the bondpads, the individual elements are basically arranged in the same way. The geometries of the wires differ only minimally. The D113 has two substrate connections on the upper edge.
https://www.richis-lab.de/logic54.htm (https://www.richis-lab.de/logic54.htm)
:-/O
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(https://www.richis-lab.de/images/logic/69x01.jpg)
The К155TЛ1 (K155TL1) is the Soviet version of the SN7413. The logo belongs to the manufacturer Planet, which produced in Novgorod. The brownish package material is typical for Soviet integrated circuits.
(https://www.richis-lab.de/images/logic/69x02.jpg)
The package contains a ceramic plate on which the die is placed.
(https://www.richis-lab.de/images/logic/69x03.jpg)
The edge length of the die is 1,37mm × 1,26mm. It is therefore slightly larger than the die in the Texas Instruments SN7413. There are test structures in three corners that allow the alignment of the masks to be evaluated. The squares on the lower edge appear to be etch markers. These can be used to monitor individual processes.
(https://www.richis-lab.de/images/logic/69x04.jpg)
A comparison with the SN7413 reveals a high degree of similarity. The most striking differences are the protective diodes at the inputs, which are located under the bondpads in the SN7413. The K155TL1 has double diodes between the inputs. In addition, four substrate contacts have been created in the K155TL1.
https://www.richis-lab.de/logic55.htm (https://www.richis-lab.de/logic55.htm)
:-/O
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(https://www.richis-lab.de/images/logic/70x01.jpg)
The Siemens FLH351 documented here corresponds to the SN7413. This part was manufactured in 1974.
(https://www.richis-lab.de/images/logic/70x02.jpg)
The dimensions of the die are 1,27mm x 1,15mm. Removing the package damaged the surface a little.
(https://www.richis-lab.de/images/logic/70x03.jpg)
A comparison with the Texas Instruments SN7413 shows that the design is almost identical. The number 13 on the right edge has been omitted and the lines from the bondpads to the circuit have been widened slightly.
It is also noticeable that a protective passivation layer has now been applied to the FLH351. This is particularly evident in the area of the bondpads. Nowadays, the passivation ends exactly at the outlines of the bondpads. Here the cutouts are very generously dimensioned. In the upper area, two bondpads share one cutout. In the lower area, the cutouts extend into the areas of the adjacent transistors.
The partially destroyed bondpads now also show more clearly the placement of the protective diodes at the inputs. These are located under the bondpads. In the SN7413, this was only partially visible in the lower left corner.
https://www.richis-lab.de/logic56.htm (https://www.richis-lab.de/logic56.htm)
:-/O
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(https://www.richis-lab.de/images/logic/71x01.jpg)
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The Texas Instruments SNJ54AS832 contains six OR gates, each with two inputs. The SN54AS832 variant is an “OR driver” that can drive up to +/-40mA at its outputs. As a 54 variant, the component is specified for the military temperature range (-55°C to 125°C). The letter J indicates that development, manufacturing, and testing comply with the MIL-STD-883 standard. The circuit belongs to the very fast “Advanced Schottky” family, as described in more detail in the context of the SNJ54AS04 (https://www.richis-lab.de/logic38.htm (https://www.richis-lab.de/logic38.htm)). The package designation is LCCC-20 (Leadless Ceramic Chip Carrier).
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The supply potentials are connected to the die via two parallel bondwires.
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The dimensions of the die are 2,5mm x 1,7mm. In the upper left corner, the metal layer contains the character string AS832A, a reference to the designation of the part. The character string AS804A in the lower left corner is interesting. It is located in a deeper layer. Apparently, the SN54AS804 forms the basis that can be reconfigured into an SN54AS832 with a different metal layer. The SN54AS804 contains six NAND drivers, each with two inputs.
This image is also available in a higher resolution: https://www.richis-lab.de/images/logic/71x04XL.jpg (https://www.richis-lab.de/images/logic/71x04XL.jpg) (13MB)
(https://www.richis-lab.de/images/logic/71x05.jpg)
The six gates are clearly visible and relatively easy to see, as the circuit was constructed with only one metal layer.
This image is also available in a higher resolution: https://www.richis-lab.de/images/logic/71x05XL.jpg (https://www.richis-lab.de/images/logic/71x05XL.jpg) (5MB)
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(https://www.richis-lab.de/images/logic/71x08.jpg)
In its “Supplement to TTL Data Book Volume 3,” Texas Instruments shows how the Schottky transistors of the AS logic family are constructed. In contrast to the S and LS families, in the AS logic ion implantation was used for doping. This allows the various doping areas to be adjusted more precisely. In addition, oxide trenches were introduced around the transistors, which reduces parasitic capacitance.
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The actual structures cannot be easily explained. At first glance, the transistors are more reminiscent of MOSFETs. Apparently, not all areas are visually distinct. Resistor strips should be located in several places. Two corresponding contacts can be seen in the upper left area. The resistor strip itself is not visible.
(https://www.richis-lab.de/images/logic/71x06.jpg)
The power transistors at the outputs look more like ordinary bipolar transistors.
https://www.richis-lab.de/logic57.htm (https://www.richis-lab.de/logic57.htm)
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(https://www.richis-lab.de/images/logic/72x01.jpg)
The Motorola MC14534 is a five-digit counter. Index C indicates the slower sorting, which can operate at a minimum of 0,25MHz. Sorting A guarantees 0,5MHz. In 1975, only these two sorts were documented. The datasheet from 1995 then only lists index B, which is similar to index A but differs slightly in certain respects. For example, the highest clock frequencies are possible at 15V, while the old variants offer the highest values at 10V. The index L stands for the ceramic package, which has unusually rounded edges compared to more modern components.
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The block diagram in the datasheet shows the exact functionality. The five cascaded counters output their values via a common BCD interface. An externally supplied clock signal controls the switching between the counters. Five outputs can be used to switch between the digits of a display.
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The dimensions of the die are 3,5mm x 3,3mm. The only marking is the character string 9KL in the lower left corner. It is a CMOS process. The five counters can be discerned. The sixth, similar area is probably the scanner that performs the multiplexing.
This image is also available in higher resolution: https://www.richis-lab.de/images/logic/72x03XL.jpg (https://www.richis-lab.de/images/logic/72x03XL.jpg) (13MB)
https://www.richis-lab.de/logic58.htm (https://www.richis-lab.de/logic58.htm)
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(https://www.richis-lab.de/images/logic/73x01.jpg)
PCF is an abbreviation commonly used by Philips. One might assume that the part number is PCF7420. In the standard logic gate nomenclature 7420 would stand for two NAND gates. In fact, however, this is a BDC/7-segment decoder. Consequently, the number sequence 7447 is the device’s designation. Given its origin, one can assume that 7420 is the datecode. 9357 could be an additional designation assigned by Philips.
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Unfortunately, the die has been slightly damaged. Its dimensions are 2,35mm x 1,69mm. The circuit is similar to the D146/D147 HFO and is described in more detail in that section (https://www.richis-lab.de/logic02.htm (https://www.richis-lab.de/logic02.htm)).
This image is also available in a higher resolution: https://www.richis-lab.de/images/logic/73x02XL.jpg (https://www.richis-lab.de/images/logic/73x02XL.jpg) (50MB)
(https://www.richis-lab.de/images/logic/73x03.jpg)
The designation NO4647 indicates that the circuit could be used with both the 7446 and the 7447. The only difference between the two types is the output voltage rating (30 V/15 V).
https://www.richis-lab.de/logic59.htm (https://www.richis-lab.de/logic59.htm)
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(https://www.richis-lab.de/images/logic/74x01.jpg)
The Hammond Suzuki XB-2 keyboard contains two specialized ICs that handle the sound generation. They are labeled DRB and MUSE. The block diagram above shows these two components in the lower right corner. DRB stands for “Digital Rotary Box.” This IC reads data from a ROM to generate sounds characteristic of a rotating speaker. MUSE stands for “Multi Stage Envelope.” This IC generates the more common signal shapes.
(https://www.richis-lab.de/images/logic/74x02.jpg)
The DRB module uses a 100-pin LQFP package. The logo belongs to Suzuki. Suzuki had acquired the rights to the Hammond brand. The designation RF5C156 suggests that the Japanese semiconductor manufacturer Ricoh produced the IC. Some Ricoh components have similar designations.
(https://www.richis-lab.de/images/logic/74x03.jpg)
The package contains a die with an edge length of 6,8mm. Thirty-six distinct rows are clearly visible, representing the required logic. Power lines for these rows run along the sides and through the center. The input and output circuitry is integrated into the frame structure.
This image is also available in higher resolution: https://www.richis-lab.de/images/logic/74x03XL.jpg (https://www.richis-lab.de/images/logic/74x03XL.jpg) (98MB)
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The markings on the die confirm that it is a Ricoh chip.
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5GV094 is the model number. The letter A could stand for a revision of the design.
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The 5GV094 is a CMOS gatearray with up to 9.400 gates and up to 154 I/Os. The minimum feature size is reportedly 1,2µm.
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The upper right corner shows the mask revisions. 03 defines the active areas. 10 forms the polysilicon for the gate electrodes. 17 and 23 are the two metal layers. 15 and 21 likely form the contacts from the metal layers to the respective underlying layers. 18 appears to create openings in the passivation layer above the bondpads.
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The number sequence 011 cannot be identified. Perhaps this is the designation for the application-specific design.
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(https://www.richis-lab.de/images/logic/74x10.jpg)
Each row has a metal frame that carries the supply voltages. The rows contain p-MOS transistors at the top and slightly shorter n-MOS transistors at the bottom. Two pairs of these transistors form the smallest unit of the gatearray (yellow). The two p-MOS and the two n-MOS transistors each share a common connection. Polysilicon strips form the gate electrodes. Each strip extends across one of the lower and one of the upper MOSFETs. In the middle section, the polysilicon is wider. This is where the gate can be contacted (green). The MOSFETs provide contact areas along their entire length (red/blue).
Despite the two metal layers, the simpler gate interconnections are visible. With oil immersion, the structures could be resolved even better.
(https://www.richis-lab.de/images/logic/74x11.jpg)
In denser areas, it is much harder to make out the wiring.
(https://www.richis-lab.de/images/logic/74x12.jpg)
The 5GV series offers several different logic gates.
(https://www.richis-lab.de/images/logic/74x13.jpg)
Each gate family, in turn, contains several variants.
(https://www.richis-lab.de/images/logic/74x14.jpg)
The structures that can be used as inputs or outputs are integrated beneath the outer metal frame.
https://www.richis-lab.de/logic60.htm (https://www.richis-lab.de/logic60.htm)
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(https://www.richis-lab.de/images/logic/75x01.jpg)
And here we have the second IC, the MUSE.
TQFP-128, Suzuki logo, another Ricoh naming.
(https://www.richis-lab.de/images/logic/75x02.jpg)
The package contains a die with an edge length of 8,5mm × 9,1mm. It is clearly also a gatearray. It has 48 logic rows. Unlike the DRB, there are surprisingly clearly defined blocks.
This image is also available in higher resolution: https://www.richis-lab.de/images/logic/75x02XL.jpg (https://www.richis-lab.de/images/logic/75x02XL.jpg) (173MB)
(https://www.richis-lab.de/images/logic/75x06.jpg)
(https://www.richis-lab.de/images/logic/75x04.jpg)
This is another Ricoh gatearray from the 5GV family. The MUSE device is based on the largest model, the 5GV161, which features up to 16.100 gates and up to 204 IOs.
(https://www.richis-lab.de/images/logic/75x05.jpg)
The same masks were used as in the DRB.
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Here, too, the number sequence 011 has been depicted.
https://www.richis-lab.de/logic61.htm (https://www.richis-lab.de/logic61.htm)
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(https://www.richis-lab.de/images/logic/76x01.jpg)
The chip documented here was found in a Canon S-60 typewriter. The labeling clearly indicates that it is a Fujitsu MB62H125 gate array.
(https://www.richis-lab.de/images/logic/76x02.jpg)
Unfortunately, the die was severely damaged during the extraction process. Its dimensions are 4,7mm x 4,5mm. The structures typical of a gate array are immediately recognizable.
This image is also available in higher resolution: https://www.richis-lab.de/images/logic/76x02XL.jpg (https://www.richis-lab.de/images/logic/76x02XL.jpg) (78MB)
(https://www.richis-lab.de/images/logic/76x03.jpg)
In the lower right corner, the designation 62H125 is just barely visible.
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The MB62H125 gate array can implement up to 900 gates and belongs to Technology H, whose speed is comparable to that of Schottky TTL.
(https://www.richis-lab.de/images/logic/76x06.jpg)
The structure of the basic elements is clearly visible. Two polysilicon strips form the gate electrodes of four MOSFETs. Each pair consists of two P-channel and two N-channel MOSFETs connected together. Two metal layers were used for application-specific wiring. With an undamaged die, it would in principle be possible to fully analyze the circuit.
(https://www.richis-lab.de/images/logic/76x05.jpg)
For the gate arrays in this family, there is a table of macros that represent various 74-series logic elements. It is interesting to note that the table also documents how many basic cells (BCs) are required to implement each logic function. For example, the 16:1 multiplexer 74150 occupies 112 basic cells.
https://www.richis-lab.de/logic62.htm (https://www.richis-lab.de/logic62.htm)
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(https://www.richis-lab.de/images/logic/77x01.jpg)
The HFO D355 is a timing circuit that allows building a time relay with only very few additional components. The block diagram above was taken from the magazine Radio Fernsehen Elektronik 5/1980, where the circuit was introduced for the first time. An oscillator generates a clock, which then passes through up to four dividers: 1024:1, 10:1, 10:1, and 6:1. Via the three inputs Ia, Ib, and Ic, the behaviour of the output can be configured within certain limits.
The device is usually designated E355. The letter E stands for an extended operating temperature range.
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The magazine RFE also shows a typical application that allows timing ranges between 0,1s and 10min. The coarse adjustment is done with the switch Sz, and the fine adjustment with the resistor Rb. If a significantly larger timing range is required, the circuit can be expanded with the divider circuit E350.
(https://www.richis-lab.de/images/logic/77x03.jpg)
The device shown here was manufactured in September 1987 (V9).
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The die measures 2,0mm × 1,4mm. Most of the circuit is implemented in I²L technology. Its structure and operation are described in more detail in the context of the CA3161 (https://www.richis-lab.de/logic22.htm (https://www.richis-lab.de/logic22.htm)).
This image is also available in higher resolution: https://www.richis-lab.de/images/logic/77x04XL.jpg (https://www.richis-lab.de/images/logic/77x04XL.jpg) (11 MB)
(https://www.richis-lab.de/images/logic/77x05.jpg)
Apparently, this is the fourth revision of the design. Below the designation, the revisions of nine masks are documented.
(https://www.richis-lab.de/images/logic/77x06.jpg)
A larger test structure contains a ring oscillator, a single transistor, and an I²L area.
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In several places, interesting capacitors can be found that use pn junctions to achieve high capacitance values.
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In the lower left corner is the oscillator of the D355. It corresponds largely to an NE555 — more precisely, a B555 (https://www.richis-lab.de/555_3.htm (https://www.richis-lab.de/555_3.htm)). In fact, a D455 was developed from this circuit, which can be considered a predecessor of the B555. However, the D455 was never produced in series.
(https://www.richis-lab.de/images/logic/77x09.jpg)
This design of the D355 was once shown on an RFE calendar.
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Here you can see an early draft of the D355. The circuit sections are arranged a bit more loosely, and more test structures are integrated.
This image is also available in higher resolution: https://www.richis-lab.de/images/logic/77x10XL.jpg (https://www.richis-lab.de/images/logic/77x10XL.jpg) (3 MB)
https://www.richis-lab.de/logic63.htm (https://www.richis-lab.de/logic63.htm)
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(https://www.richis-lab.de/images/logic/78x01.jpg)
The D350 is better known as the E350, with the “E” simply denoting the extended operating temperature range. The D350, along with the block diagram shown above, was featured in the magazine "Radio Fernsehen Elektronik" (5/1980). The chip offers several divider stages. In the upper section, there is a 10:1 divider, a 6:1 divider, and another 10:1 divider. In the lower section, there is a 24:1 divider and two 2:1 dividers.
(https://www.richis-lab.de/images/logic/78x05.jpg)
The D350 was replaced by the D351 relatively quickly. The first mention of the D351 appears in the August 1982 issue of the "Radio Fernsehen Elektronik". The two components are not fully interchangeable, as the pin assignments have changed. In addition, the inputs and outputs in the upper divider chain have been separated, allowing for more flexible use.
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The D351 uses I2L technology, as described in more detail in the CA3161. "Radio Fernsehen Elektronik" shows the design of a single 2:1 divider that requires only five of these I2L transistors. The line above the upper T input is a misprint. The transistors are operated with different injector currents, resulting in different switching speeds. The filled circles indicate the slower transistors. Under the title “I2L Circuit Technology” Radio Fernsehen Elektronik 8/1977 features an article describing how the different switching speeds can alternatively be achieved by using PNP transistors of different sizes in the I2L structures.
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A typical application for the D351 is to use it in combination with the D355 timer circuit, which allows for time periods of up to 40 days.
(https://www.richis-lab.de/images/logic/78x04.jpg)
This IC was produced in March 1986 (U3).
(https://www.richis-lab.de/images/logic/78x06.jpg)
The die measures 2,26mm x 1,55mm. This appears to be the first revision of the design. The circuit consists primarily of I2L technology.
This image is also available in higher resolution: https://www.richis-lab.de/images/logic/78x06XL.jpg (https://www.richis-lab.de/images/logic/78x06XL.jpg) (45MB)
(https://www.richis-lab.de/images/logic/79x01.jpg)
This image shows a D350. The layout of the circuit blocks is similar to that of the D351.
(https://www.richis-lab.de/images/logic/79x02XL.jpg)
Here is an early version of the D350 featuring a large number of test patterns.
This image is also available in higher resolution: https://www.richis-lab.de/images/logic/79x02XL.jpg (https://www.richis-lab.de/images/logic/79x02XL.jpg) (3MB)
https://www.richis-lab.de/logic64.htm (https://www.richis-lab.de/logic64.htm)
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(https://www.richis-lab.de/images/logic/80x01.jpg)
The Sinclair ZX81 is a home computer based on the Z80 processor.
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(https://www.richis-lab.de/images/logic/80x03.jpg)
The processor used here is a D780, NEC’s version of the Z80. The Motorola ZCM38818 is a mask-programmed 8kB ROM based on the MCM68364. Alongside it are two Motorola MCM21L14 chips, providing 1kB of RAM. At the top left, the ULA2C210E gate array handles various functions. The integrated circuit generates the system clock and controls peripheral modules, specifically the video interface. The gate array also manages the memory areas.
(https://www.richis-lab.de/images/logic/80x04.jpg)
The ULA2C210E is an updated version. Previously, the ZX81 used a gate array called the ULA2C184, which had some functional limitations.
(https://www.richis-lab.de/images/logic/80x13.jpg)
The Ferranti “Quick Reference Guide” shows that the ULA2C gate array is the smallest member of a family capable of operating at 20 MHz. The device offers up to 450 gates.
(https://www.richis-lab.de/images/logic/80x05.jpg)
The die size of the ULA2C210E is 4,0mm. The large logic area is clearly visible. Power is supplied solely via a frame structure. The input and output circuits are located on the outer edges. Overheating is clearly visible on the right edge.
This image is also available in higher resolution: https://www.richis-lab.de/images/logic/80x05XL.jpg (https://www.richis-lab.de/images/logic/80x05XL.jpg) (214MB)
(https://www.richis-lab.de/images/logic/80x06.jpg)
For this image, the last remnants of the package material were removed. The surface has suffered some damage, but with these two images, it would now be possible to fully document the circuit.
This image is also available in a higher resolution: https://www.richis-lab.de/images/logic/80x06XL.jpg (https://www.richis-lab.de/images/logic/80x06XL.jpg) (215MB)
(https://www.richis-lab.de/images/logic/80x07.jpg)
(https://www.richis-lab.de/images/logic/80x08.jpg)
(https://www.richis-lab.de/images/logic/80x09.jpg)
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Various test patterns and character strings are incorporated into the corners. Several masks are displayed in the upper-left corner. The squares apparently allow you to check the alignment of the masks relative to one another.
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The damage to the right edge is due to a severe electrical overload. It is possible that the electrical overload was merely a secondary fault caused by excessive heat. The gate array is known to fail in this way. This is reportedly due to a 75% utilization rate. Ferranti is said to have designed the gate array for a maximum utilization of only 50%: https://www.retroisle.com/sinclair/zx81/Technical/Hardware/custom_ula.php (https://www.retroisle.com/sinclair/zx81/Technical/Hardware/custom_ula.php)
(https://www.richis-lab.de/images/logic/80x12.jpg)
There is very little information available about the ULA2C gate array. The description above is taken from the “Quick Reference Guide.” Most gate arrays are based on CMOS elements. They consist of double rows in which NMOS and PMOS transistors are arranged side by side. The ULA2C, on the other hand, is based on bipolar transistors. To form gates from these, additional components are required. This may have been one reason why the smallest logic blocks were designed as more or less square, relatively large cells.
As basic elements, one can choose between RTL, CML, or buffered CML. RTL stands for “Resistor Transistor Logic.” The first logic circuits were built using this technology. It is essentially based on an NPN transistor with a collector resistor. CML stands for “Current Mode Logic.” In this case, the logic levels are transmitted not as voltage signals but as current signals. The cell shown here represents a buffered CML. The schematic shows the included blocks, which can generally be connected in any configuration. Transistors T1–T4 form two differential amplifiers and are integrated in pairs accordingly. TS and T6, which should probably be labeled T5 and T6, represent the buffer stage. In addition, there is the current sink Tcs with multiple inputs.
(https://www.richis-lab.de/images/logic/80x14.jpg)
Here you can see an unused cell of the ULA2C210E.
(https://www.richis-lab.de/images/logic/80x15.jpg)
It can be seen that the ULA2C210E is based on CML cells. The substrate is p-type and distributes the ground potential. Within the cell, there is a wide contact to the substrate. The areas between the cells are n-type and conduct the positive supply potential. The corresponding contact is located between the two resistors at the top right. There are no additional supply lines within the logic area. In the upper right corner, three p-doped strips are incorporated into the n-doped region. These three strips represent the three resistors of the circuit.
Where the active elements are located, the full-area n-doping has been omitted and isolated n-doped regions have been incorporated. They serve as collector regions and as cross-connections. Typically, the collector doping is less concentrated than the base doping. Here, this appears to be different, as otherwise the cross-connections would already present a higher resistance than the actual resistors. The collector doping must also be high because it serves to distribute the supply potential across the region. The two transistor pairs Q1/Q2 and Q3/Q4 share a collector region. Transistor Q5 acts as the current sink. There, two emitter regions are located within a common base region.
Each cell thus provides two NOR gates, each with two inputs. There are 15x15 cells on the die. This results in a total of 450 gates, as specified. In CML, signal processing is often differential. That is not the case here. The single output is located above the input transistors. However, the circuit shows that the node below the transistors is also used as an output.
A striking feature of the circuit is the NPN transistor operating inverted in the current sink. Transistors can be operated inverted, but many parameters are then significantly worse. This is because the collector and emitter are n-doped to different degrees in order to optimize the electrical properties. In this circuit, however, inverted operation can be quite useful. As already mentioned, the collector appears to be unusually heavily doped. As a result, the collector and emitter are much more similar than in a conventional transistor.
The disadvantages of an inverted operation include a significantly reduced reverse voltage, a lower cutoff frequency, and negligible current gain. With a supply voltage of 5 V, the reverse voltage is not a critical factor. In the case of a current sink, the cutoff frequency is irrelevant. The low current gain is also not a problem here, as long as the power dissipation of the current sinks is acceptable. The reduced saturation voltage of an inversely operated transistor, on the other hand, could be a relevant advantage. In any case, it is practical to be able to implement two current sinks in a very small area, for which two transistors would otherwise be required. In addition, the current fluctuates less with the applied voltage.
(https://www.richis-lab.de/images/logic/80x16.jpg)
Here you can see a cell integrated into the circuit. The first gate (yellow) is used simply as an inverter. The second gate (cyan) is a NOR gate with two inputs and two outputs.
https://www.richis-lab.de/logic65.htm (https://www.richis-lab.de/logic65.htm)
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(https://www.richis-lab.de/images/logic/81x01.jpg)
The Texas Instruments SN97145 is an integrated circuit that does not appear in any official parts list. The chip is found in the TI-1500 calculator (https://www.richis-lab.de/calc13.htm (https://www.richis-lab.de/calc13.htm)), which is sold by Texas Instruments. It is most likely a custom design that was never made available to the public.
(https://www.richis-lab.de/images/logic/81x02.jpg)
The die measures 1,7mm × 1,2mm. The number 27882 refers to the SN27882, which is documented here: http://www.datamath.org/Chips/SN75497.htm (http://www.datamath.org/Chips/SN75497.htm) The minor differences do not appear to be electrically significant. This leaves open the question of why Texas Instruments assigned a new designation to the SN97145.
In the lower section, there are seven drivers with open-collector outputs. The driver stages arranged above them consist of a parallel connection of a transistor and two diodes.
https://www.richis-lab.de/logic66.htm (https://www.richis-lab.de/logic66.htm)
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