Variable DC offset Removal

[sanwal209]

Hi Guys,

I am trying to remove variable dc offset from a signal of 1Hz. I have tried two approaches one dc blocking capacitor and dc servo offset removal method. As dc offset changes with block capacitor it takes huge time for the signal to settle down. I decrease the settling time 10 times less with dc servo method but it still not enough. DC offset is caused by battery and with load variation on battery, there will sudden voltage dips.

Can you guys recommend any fast response filter to block varying dc voltage.

Thanks

[KaneTW]

Do you have a way to measure the DC offset without the signal?

[sanwal209]

So far No. If you recommend any circuit for it that would be great. With that we will be able remove the dc offset in software.

[KaneTW]

Without knowing how your DC offset changes it's a bit hard to suggest a filtering method. Do you have oscilloscope screenshots you can post?

[b_force]

Higher order filtering will also help a lot

[sanwal209]

Project scope is to design an isometer uses in EV. In isometer, I am injecting +-40V 1Hz square wave to chassis.  At the end of system I have ac signal and dc offset added by HV battery. I have attached schematics for more clear understanding.

In schematics, i am measuring current via R32 which is inversely proportional to the isolation resistance. I am measuring voltage at VF1 and VF3, VF1-VF3 will be voltage across isolation resistance. In this way i am measuring isolation resistance. AC signal injection method is used because this system should be independent of Battery voltage. As i mentioned before, if battery voltage changes HPF will take huge amount of time to settle down.

Please have at schematics

[ebclr]

Read thios site  https://youtu.be/Ep4r-wD7PPs

Take special attention to the section subtrator

[jbb]

I think you’ve got your work cut out for you at 1Hz - filters need to be very slow.  Is that a fixed requirement?

If you’re requirement is something like ‘measure isolation resistance at a rate of 1 Hz,’ that does not mean you have to use a 1Hz test wave. You could instead use bursts of, say, 20 Hz (subsonic) or some hundred Hz (provided you don’t have trouble with capacitive effects or accidental accoustic output).  A 20 Hz probe waveform would be much easier to filter than 1 Hz.  A 200 Hz probe waveform might be high enough to avoid a lot of flicker (1/f) noise in the op amp.

Maybe a 2 stage approach could be helpful:
1) Cook up some kind of common mode amplifier (instead of the usual differential amp) to reject changes in the main battery voltage by analog means.
2) Implement a synchronous detector (in analog or software) to selectively measure your probe signal. This is essentially a frequency mixer which shifts your probe signal down to a DC level that you can simply low pass.

Don’t forget to consider ESD, conducted noise and radiated noise in your design.

Finally, if battery voltage variations are a particular problem and cause false tripping, you could use some kind of CDMA trick to make a complex probe waveform with very low correlation to any fixed frequency.

[David Hess]

Measure the peak positive and peak negative voltages.  Subtract the average or an adjustable ratio between them.

Incidentally, this is how the oscilloscope peak-to-peak triggering works.

[b_force]

Is there a way or a point in the circuit were you can get only the DC offset?
(so without the 1Hz signal)

Because than you can simply use a differential to single ended amplifier to cancel out the DC

[coppice]

I assume the drift rate of the DC is slow compared to 1Hz. If it isn't, the drift and the signal of interest will merge to some extent.

Usually its hard to do this kind of thing well, because you lack local access to the exact timing of the source signal at the point where the analysis is being done. That means you need a filter with a sharp cutoff below 1Hz to get an accurate DC estimate, while responding reasonably fast to changes in that DC level. Since you are generating the pulses not far from where you are analysing the received signal, you should be able to get the exact timing of the pulses where the analysis takes place. If you integrate over each cycle you can estimate the DC cycle by cycle, and subtract it from that cycle. If you are going this in an analogue manner you probably won't have an easy way to store the cycle of waveform while you estimate its DC content. If the DC doesn't drift too fast you can use the estimate from each cycle to subtract from the following cycle. If you are doing things digitally it should be easy to subtract the DC estimate from the actual cycle it was estimated from..

[b_force]

Just brainstorming here;

Another idea is to apply a notch at 1Hz, so you're left with everything except your 1Hz signal.
Than substract that notched signal from the total signal (1Hz plus variable DC)

[coppice]

Just brainstorming here;

Another idea is to apply a notch at 1Hz, so you're left with everything except your 1Hz signal.
Than substract that notched signal from the total signal (1Hz plus variable DC)

How are you going to make a deep notch with no funky phase behaviour, so that it subtracts nicely from the original signal?

[b_force]

Just brainstorming here;

Another idea is to apply a notch at 1Hz, so you're left with everything except your 1Hz signal.
Than substract that notched signal from the total signal (1Hz plus variable DC)

How are you going to make a deep notch with no funky phase behaviour, so that it subtracts nicely from the original signal?

Short answer;
DSP or FPGA
I think even a ucontroller can do is, it is such a low frequency, so you don't need a high sample rate.

But if you have to use an anlog circuit.
Well the phase issue is only around the notch.
So my first question is, would it even be an issue at all?

[coppice]

Just brainstorming here;

Another idea is to apply a notch at 1Hz, so you're left with everything except your 1Hz signal.
Than substract that notched signal from the total signal (1Hz plus variable DC)

How are you going to make a deep notch with no funky phase behaviour, so that it subtracts nicely from the original signal?

Short answer;
DSP or FPGA
I think even a ucontroller can do is, it is such a low frequency, so you don't need a high sample rate.

The issue is not the implementation. Its the maths.

But if you have to use an anlog circuit.
Well the phase issue is only around the notch.
So my first question is, would it even be an issue at all?

You have to get quite a long way from the notch before the phase settles enough to have only a minor effect on what is being subtracted. In that area subtracting the wrong thing will distort the waveform of interest.

[b_force]

Just brainstorming here;

Another idea is to apply a notch at 1Hz, so you're left with everything except your 1Hz signal.
Than substract that notched signal from the total signal (1Hz plus variable DC)

How are you going to make a deep notch with no funky phase behaviour, so that it subtracts nicely from the original signal?

Short answer;
DSP or FPGA
I think even a ucontroller can do is, it is such a low frequency, so you don't need a high sample rate.

The issue is not the implementation. Its the maths.

But if you have to use an anlog circuit.
Well the phase issue is only around the notch.
So my first question is, would it even be an issue at all?

You have to get quite a long way from the notch before the phase settles enough to have only a minor effect on what is being subtracted. In that area subtracting the wrong thing will distort the waveform of interest.

With FIR filters you can basically have no phase issues at all, so I don't see the problem?
But digitally you can do a lot of stuff.

Btw just a simple low pass filter will introduce phase issues as well?

[capt bullshot]

Project scope is to design an isometer uses in EV. In isometer, I am injecting +-40V 1Hz square wave to chassis.  At the end of system I have ac signal and dc offset added by HV battery. I have attached schematics for more clear understanding.

This literally cries to apply correlation / synchronous rectifying / lock-in-amplifying (choose whatever buzzword you like
You know the excitation, so you can use this to demodulate the signal from all the noise around.

Build an integration stage: At the start of the first cycle, reset your integrator. Multiply the measured signal by the excitation state (can be +1 and -1 here) and integrate the multiplication result. Low pass or box car filter the integrator output over n cycles, and there's your result.

[sanwal209]

First of all thank you guys for overwhelming support. I will try to give answers one by one.

@jbb I cannot use high frequency signal because of high stray capacitance parallel isolation resistance. Yes, i will feed excitation signal to mcu for synchronization. Offcourse there will be TVS diode for ESD protection. Regarding common mode amplifier technique can you please explain it a bit further?

@David Hess I will simulate this and will get back to you.

@coppice DC drift depends how hard driver is accelerating the vehicle.I have discussed this with the software guy, he suggested that we can use moving average filter. That could be a potential solution.

@b_force Yes, phase change will be an issue as this system will also have to measure capacitance parallel to isolation resistance by detecting phase change. I am trying as much as possible to resolve these things on HW and last resort will be the Firmware.


@capt bullshot can you please show an example circuit diagram for better understanding.

Another issue i noticed today is that as battery have small internal resistance so the change of Positive isolation resistance will effect the output of negative isolation resistance

[IDEngineer]

Forgive me for not having the time to dig deeply into your problem, but what I think I got from reading your responses to others is that your output 1Hz square wave is riding on a DC offset from the battery, and the battery voltage may vary as its load changes.

Doesn't that imply that the battery voltage can be measured independently? That there's some point at which all the separate cells are tied together? If the battery's ESR isn't too high (which it shouldn't be for an EV application given the peak current requirements) then presumably your 1Hz square wave doesn't modulate the actual battery voltage. If that's true, then you should be able to take the actual battery voltage and do a simple subtraction with an opamp to remove the bias from your 1Hz output waveform. Might take some scaling to calibrate it, but once dialed in the battery's "variable" output voltage would act as an input to an opamp and be subtracted from your output waveform that contains the same battery voltage as an undesired DC offset. As the battery voltage varies, so does your DC offset - and so too does the input to the opamp. No filters, no phase problems, no firmware.

Again, I apologize for not digging deeper, perhaps there's a reason you can't do this, but from the 100,000 foot view this is where I'd start.

[capt bullshot]

These papers provide some explanation of synchronous demodulation:

http://www.analog.com/media/en/analog-dialogue/volume-49/number-2/articles/low-power-synchronous-demodulator.pdf
http://www.analog.com/media/en/analog-dialogue/volume-48/number-4/articles/synchronous-detectors-facilitate-precision.pdf

For your planned excitation frequency, I'd you won't need any HW, just feed the signal into your uC's ADC and do the rest in SW.
For quicker respose, I'd increase the excitation frequency.

[MasterT]

The idea is not to filter out DC, but rather filtering frequency of interest, 1 Hz in this case.
Hardware solution (notch filters, synchronous detectors) is good approach anywhere else but not for 1 Hz. To get meaningful precision it would takes hours if not a days.
The right way is a software, FFT in particular. Small uCPU, like arduino UNO (AtMega328) running 256 samples per second, than
 FFT calculation may provides close to 14-bits (0.01%) precision in just 1 second (!) period. Moreover, since the feed is square wave, FFT outputs may contain useful information about harmonics distribution with their phases.