I2S digital expansion port, wondering about EMI

[jrs45]

I have a audio power amplifier designed, and I'm considering adding an I2S port (FFC) to drive a second board.  These signals are ~25MHz (but may have a sharp risetime). 3.3V

The most convenient connector position is at the end of ~2" traces that carry all these signals.  But wouldn't these high speed, unterminated traces, all turn into antennas transmitting all kinds of noise?  Or is it very low because the current is effectively zero?  (I'm not sure what the RF impedance would be of each trace over a ground plane in a 4layer PCB, maybe I should figure that out.)

edit: Since it's on the outer layer of a 4 layer pcb, 8mil tracks with 9mil thick dielectric, it's 74 ohms stripline for each signal line.

[Benta]

The standard way of doing this on a 667 MHz DDR bus is series termination at the receiving end (18 ohms) to dampen ringing. At 25 MHz, I wouldn't worry too much.

[Bassman59]

I have a audio power amplifier designed, and I'm considering adding an I2S port (FFC) to drive a second board.  These signals are ~25MHz (but may have a sharp risetime). 3.3V

The most convenient connector position is at the end of ~2" traces that carry all these signals.  But wouldn't these high speed, unterminated traces, all turn into antennas transmitting all kinds of noise?  Or is it very low because the current is effectively zero?  (I'm not sure what the RF impedance would be of each trace over a ground plane in a 4layer PCB, maybe I should figure that out.)

edit: Since it's on the outer layer of a 4 layer pcb, 8mil tracks with 9mil thick dielectric, it's 74 ohms stripline for each signal line.

I did something similar ages ago, forwarding I2S plus the modulator clock between boards. I used a quad LVDS driver DS90LV048AA and its complementary receiver DS90LV047A. I used standard RJ45 jacks (not Ethernet MagJacks) and the connector pinout was the same as Ethernet so off-the-shelf CAT5 patch cords could be used. To help meet EMC I put ferrite beads on the output signals and we had clamp diodes on the inputs. MCLK was the fastest signal at 24.576 MHz. It worked well.

[jrs45]

Thanks for such a thorough response!

* You say the edge rates are very fast.  It may be that they don't need to be anywhere near that fast. 

Correct, I have inserted series resistors (25 ohm) at the source for this purpose, so perhaps that will be sufficient.  From my probing the corners look reasonably round.

If the lines stay tightly coupled to their reference plane and have consistent impedance (74R or whatever) over their length then the microstrip lines themselves shouldn't
radiate much or create much EMI / SI problems as long as the lines are terminated at the source or destination if they're appreciably long compared to the edge times.
..
To prevent EMI from aggressor traces to other traces, avoid running closely parallel potential victim traces to noisy toggling lines.

Yes, these are running along the top and bottom sides, with unbroken ground areas directly under them.  Vias have ground vias next to them too.  I've also kept any sensitive analog traces well away from this.  The parallel traces are all clock, I2S, I2C.  I think I have followed good layout practice, it was really the inclusion of these "long" traces that (usually) don't go anywhere but an empty connector that I'm concerned about.

For interconnect don't rely on just a small number of "ground" and "VCC" pins if you have several fast clocked signals.  In a cable / connector run a "ground" and "power" signal approximately next to each single ended fast toggling signal so that the return current for the signal will be approximately adjacent to the signal line in path and the loop area of the signal and its return conductor is minimized.

Yes, I've included GND on every other pin of the FFC connector for this reason.

Mind your return paths and don't route fast AC signals over discontinuities / holes / splits in the relevant return path, so just as you have a continuous signal track, right
over / under it have a continuous return reference plane for non-differentially routed/encoded signals.

Howard Johnson's book "high-speed digital design" would be useful to learn about EMC / SI, and Ott's "electromagnetic compatibility engineering" for instance.
And "right the first time":
https://www.thehighspeeddesignbook.com/

I've done all of this!  And I've read all of those sources, and they're excellent.  I'm also watching everything I can find from Bogatin and Hartley.  I think I've got it all correct, it's just the matter of leaving these "long" energized traces that are unterminated that I was worried about.  Perhaps that worry is not well justified as long as the rest of the layout is done properly.

I just didn't want these things to become antennas.

[jrs45]

Nice.  This would be for another small power amp nearby (~6") so I don't think I need to get this complicated.  Did you place the ferrite beads in series with the signals?  Is clamp diodes the right solution to prevent ringing?  (Seems hamfisted but maybe not?)

I did something similar ages ago, forwarding I2S plus the modulator clock between boards. I used a quad LVDS driver DS90LV048AA and its complementary receiver DS90LV047A. I used standard RJ45 jacks (not Ethernet MagJacks) and the connector pinout was the same as Ethernet so off-the-shelf CAT5 patch cords could be used. To help meet EMC I put ferrite beads on the output signals and we had clamp diodes on the inputs. MCLK was the fastest signal at 24.576 MHz. It worked well.

[jrs45]

Thanks!  There will be no cable connected normally, and I can't shut these off (they drive another amp channel normally, this is for an extra identical channel receiving I2S in parallel).  It's just the trace stubs I'm worried about, not a dangling cable.