Author Topic: Low EMI SMPS - How to design to pass FCC  (Read 1698 times)

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Offline depotTopic starter

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Low EMI SMPS - How to design to pass FCC
« on: December 07, 2019, 05:26:17 am »
I have a set of projects focused around battery powered applications, so buck-boost or SEPIC topology I think. Output voltage is the standard 3.3v for processors, also an LTE chip, maybe a few amps burst peak output current but average much less. The batteries might be lithium primary cells, 3 alkaline, lithium rechargeable, all that annoying range that could be above or below 3.3v. So far it looks really cool, but bringing things together can go haywire.

There are all kinds of white paper on this kind of design. I don't see as many "maker" level tutorials, but videos are there. I'm trying to eat it up.

I really like this "silent switcher" technology, but it's only for buck topology. https://www.analog.com/en/products/landing-pages/001/silent-switcher.html

Otherwise I see that slew rate could be important. Picking a lower frequency sounds helpful. Silent switcher has a paper about making another "hot current loop" of opposite polarity to cancel out the first one in far-field. It also sounds like some of the new technology works against my by sacrificing EMI for high efficiency, small size, and lower cost. Everyone here says low noise is the most important, design it in from the start. Other engineers have a lot of trouble with it, sounds like.

Does anyone just slap on a metal shield? I hear that also doesn't tend to work.

So share some tips with a greenhorn please! Or your own horror stories if you like.
 

Offline T3sl4co1l

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Re: Low EMI SMPS - How to design to pass FCC
« Reply #1 on: December 07, 2019, 09:03:41 am »
So, common ground, just a converter, not an isolator?

The big problems happen when voltage is generated between cables, which act as antenna elements.  That is, common mode noise.

On a common ground (say a three terminal converter, Vin, GND, Vout), common mode is limited by how well filtered Vin and Vout are with respect to GND, and by what ground loop voltage appears between the two GNDs if applicable.

Ideally you arrange the connections so they are on one side, in a row, Vin, GND, Vout, so the loop between the two grounds has zero length.  A pointlike connection.  There can't be any voltage drop between grounds, and you're safe, limited only by the filters.

Even easier if you don't have wires at all.  The worst you can do is have a voltage drop across the device itself, say from the battery end to the radio module end, or, however it's laid out.  You can still have EMC problems, but they will be limited to high frequencies, and you may not need to address grounding or snubbing but just put in some ferrite beads (mind, the amount of stuff that might need to be ferrite-beaded in such a situation might be much worse than fixing it properly ;D ).

Switching frequency doesn't matter much; higher frequency is generally desirable, for miniaturization.  Just shop for regulators or controllers in the V,I range you need.

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Offline MagicSmoker

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Re: Low EMI SMPS - How to design to pass FCC
« Reply #2 on: December 07, 2019, 12:21:10 pm »
Output voltage is the standard 3.3v for processors, also an LTE chip...

What do you need low noise for, then? Or do you simply mean, "low enough noise to pass FCC?" The former would apply if you have some sensitive analog circuits and/or an ADC running at 16b or greater precision; the latter generally always applies.

Most batteries dislike pulsating current loads so converter topologies with relatively smooth input current are preferred, such as the boost-derived converters like the boost, Cuk (aka boost-buck) and SEPIC. Loads that are sensitive to noise will do better with converters that have relatively smooth output current, like the buck-derived types such as the buck, Zeta, forward, bridge, push-pull, etc.

Note that the buck-boost - aka, non-isolated flyback - has both pulsating input and output currents so nobody is happy, and it inverts polarity to boot. That said, the SEPIC converter is the most difficult topology to stabilize (4th order + a right half plane zero), often requiring lowering the loop bandwidth down below 1/500th of the switching frequency. This might not be a good choice for your application with its wild load swings unless you can afford to throw lots of output capacitance into the mix.

An alternate to the SEPIC is the Zeta converter (basically the buck-derived version of the boost-derived SEPIC), which is still 4th order but doesn't have the RHPZ. The switch requires high-side drive, however, which does somewhat limit your choice of controller ICs to those that have a charge-pump (aka - bootstrap) driver (or you need to use an external driver IC). A really good comparison of the SEPIC and Zeta is on Linear Technology's Analog Devices' website: https://www.analog.com/en/technical-articles/the-low-output-voltage-ripple-zeta-dc-dc-converter-topology.html

I've used the SEPIC to supply 24V at up to 3A over a 2:1 input voltage range and while it did get the job done, it required about 4x the output capacitance to make up for its very poor transient response (aka - low loop bandwidth). Fortunately, the client decided after evaluating the prototype product this converter was used in that they didn't need such a wide input voltage range and I simply ripped it out entirely; I never did trust the thing to not break out into a destructive oscillation at some combination of line and load.

 

Offline T3sl4co1l

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Re: Low EMI SMPS - How to design to pass FCC
« Reply #3 on: December 07, 2019, 06:56:28 pm »
That said, the SEPIC converter is the most difficult topology to stabilize (4th order + a right half plane zero), often requiring lowering the loop bandwidth down below 1/500th of the switching frequency.

Who the hell uses voltage mode control in this day and age?

FYI, the coupling capacitor doesn't affect switching or loop response, as long as it's dimensioned appropriately, and well damped if possible.

Tim
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Offline MagicSmoker

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Re: Low EMI SMPS - How to design to pass FCC
« Reply #4 on: December 07, 2019, 10:22:18 pm »
That said, the SEPIC converter is the most difficult topology to stabilize (4th order + a right half plane zero), often requiring lowering the loop bandwidth down below 1/500th of the switching frequency.

Who the hell uses voltage mode control in this day and age?

Ahem... I didn't assume a control scheme. I also didn't mention the complications/benefits of (usually loosely) coupling the two inductors. In fact, I didn't mention a lot of things in a jaunty little forum post...  :P

That said, CMC might only reliably eliminate one inductor from the transfer function (theoretically you can take both out at the same time, but this is a case where theory and practice don't align too well).

FYI, the coupling capacitor doesn't affect switching or loop response, as long as it's dimensioned appropriately, and well damped if possible.

I always dread disagreeing with you on anything, but in my (limited, but at least non-zero) experience with the SEPIC it is quite difficult to avoid LC resonances between Cc and the two inductors, even more difficult if the inductors are coupled (hence the usual advice to loosely couple them - ie, have a lot of leakage), and damping requires Cc either have more ESR than is favorable for efficiency (ie - series damping) or a rather sizeable DC blocking capacitor for a shunt damping resistor (>4x Cc, to as much as 10x Cc).

There's good reasons why the Cuk, SEPIC, and Zeta converters are rarely used in commercial products (though arguably a good chunk is due to general unfamiliarity).

 

Offline depotTopic starter

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Re: Low EMI SMPS - How to design to pass FCC
« Reply #5 on: December 07, 2019, 11:52:52 pm »
Later on, maybe isolation will be interesting for a line power version of this thing. Oh, and there will be sensors later.

But for now the real #1 spook is just passing FCC tests. I was hired recently and they had many projects where EMI was just too much.

There will be a short wire connection between a power supply PCB and a controller with LTE/WiFi/Bluetooth module parts.
 

Offline T3sl4co1l

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Re: Low EMI SMPS - How to design to pass FCC
« Reply #6 on: December 08, 2019, 02:37:28 am »
Ahem... I didn't assume a control scheme. I also didn't mention the complications/benefits of (usually loosely) coupling the two inductors. In fact, I didn't mention a lot of things in a jaunty little forum post...  :P

It's the magnitude that implies the assumption -- if it were say 1/3, that might be a typical placement for the common mode resonance; 1/100th can basically only be with filter components included, and 1/5th again of that implies a voltage mode control.

I can't actually think of any other justification for such a constraint right now? :-//


Quote
That said, CMC might only reliably eliminate one inductor from the transfer function (theoretically you can take both out at the same time, but this is a case where theory and practice don't align too well).

CMC..?

Whose theory?  If it doesn't align well, it must not be very good. :P


Quote
I always dread disagreeing with you on anything, but in my (limited, but at least non-zero) experience with the SEPIC it is quite difficult to avoid LC resonances between Cc and the two inductors, even more difficult if the inductors are coupled (hence the usual advice to loosely couple them - ie, have a lot of leakage), and damping requires Cc either have more ESR than is favorable for efficiency (ie - series damping) or a rather sizeable DC blocking capacitor for a shunt damping resistor (>4x Cc, to as much as 10x Cc).

Hmm, I've had zero problem with them, treating them as the usual (e.g. peak or average current mode flyback) and not being particularly careful with the coupling.

Is it because I never use uncoupled inductors?  Seems superfluous to me; I think I would go for buck-boost (inverting) or "flying inductor" (Vin <> Vout) if I can't get a coupled inductor of adequate rating.

Have I been playing too fast and loose with these?  I haven't sat down and done an analysis, and a 4th order transfer function sounds pretty awful.  (Though I'm pretty sure that should be 4th with a near total pole-zero cancellation, so it's overall more like 2nd order, like the rest?)


Quote
There's good reasons why the Cuk, SEPIC, and Zeta converters are rarely used in commercial products (though arguably a good chunk is due to general unfamiliarity).

The requirements are simply uncommon, AFAIK.

What common applications require Vin <> Vout?  A lot of things will simply deal with the variation (e.g., 3-4.2V Li Ion) or choose an upper or lower limit (say, boosting to 5 or 10V for driving LEDs or electromechanical; or bucking to 2.5V or less for a somewhat lower-than-traditional logic supply).

I've certainly used them infrequently; and that's with smaller quantity products (~1000s) where the cost of a coupled inductor doesn't really matter.  I don't know that I've seen one in anything I've taken apart, though that's not a huge sample.

Tim
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Offline Tomorokoshi

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Re: Low EMI SMPS - How to design to pass FCC
« Reply #7 on: December 08, 2019, 05:48:01 am »
I used this:
https://www.digikey.com/products/en?keywords=LT3958EUHE%23TRPBFCT-ND

in SEPIC mode, 1 MHz switching frequency, circuit designed for around 18 W. Originally failed conducted emissions (Class A, industrial) by 12 dB on the DC power input when it had only a 10 uF ceramic input capacitor. Added 10 uF electrolytic input capacitor, passed with 14 dB of margin at the 1 MHz.

None of the 1 MHz switching frequency shows up on conducted emissions through the AC-powered DC supply.
 

Offline MagicSmoker

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Re: Low EMI SMPS - How to design to pass FCC
« Reply #8 on: December 08, 2019, 12:52:43 pm »
Ahem... I didn't assume a control scheme. I also didn't mention the complications/benefits of (usually loosely) coupling the two inductors. In fact, I didn't mention a lot of things in a jaunty little forum post...  :P

It's the magnitude that implies the assumption -- if it were say 1/3, that might be a typical placement for the common mode resonance; 1/100th can basically only be with filter components included, and 1/5th again of that implies a voltage mode control.

I can't actually think of any other justification for such a constraint right now? :-//

Well, the RHPZ is usually what drives the crossover frequency that low rather than the actual control scheme, but upon reviewing my old project files (this was from 2013) it seems I used the infernal TI TPS40211 controller IC (which, AFAICT, is just the AEC-qualified version of the damnable TPS40210). Back then I thought this was a great and versatile chip, but after using it a few more times over the subsequent years I have stricken it - and any other TPS chip - forever from consideration because of intractable instability that I suspect is from an overly noise-sensitive current sense input. Hence that generic admonition I gave to drop the crossover frequency to 1/500th of the switching frequency might have more to do with the misery I experienced with this chip rather than with the SEPIC in general.

But yes, that is something you'd expect with a VMC converter and/or really trying to stay away from a RHPZ.

Quote
That said, CMC might only reliably eliminate one inductor from the transfer function (theoretically you can take both out at the same time, but this is a case where theory and practice don't align too well).

CMC..?

Whose theory?  If it doesn't align well, it must not be very good. :P

Sorry - CMC = Current Mode Control; VMC = Voltage Mode Control.

But as for theory vs. reality, a favorite example of mine is the dawning realization in the late 90's that injecting a little bit of the clock ramp into the current sense input of a CMC controller can improve its noise tolerance at light loads and eliminate subharmonic oscillation at heavy loads. Eventually theory worked out the reasons for using so-called slope compensation, but only after the fact, not before it.

That said VMC with input feed-forward and pulse-by-pulse current limiting is a worthy contender to CMC with slope-compensation, particularly when dealing with wide input voltage and load ranges (CMC only indirectly achieves input FF as a result of the slope of the current sense signal changing with input voltage).

Quote
...the SEPIC it is quite difficult to avoid LC resonances between Cc and the two inductors, even more difficult if the inductors are coupled...

Hmm, I've had zero problem with them, treating them as the usual (e.g. peak or average current mode flyback) and not being particularly careful with the coupling.

Is it because I never use uncoupled inductors?  Seems superfluous to me; I think I would go for buck-boost (inverting) or "flying inductor" (Vin <> Vout) if I can't get a coupled inductor of adequate rating.

No, same here - I only used off-the-shelf coupled inductors (IIRC, Bourns makes a series with intentionally high leakage for SEPICs). Then again, I only have a sample size of 2 SEPIC designs, and one of those was modestly modified from an LT app note so doesn't really count.

Have I been playing too fast and loose with these?  I haven't sat down and done an analysis, and a 4th order transfer function sounds pretty awful.  (Though I'm pretty sure that should be 4th with a near total pole-zero cancellation, so it's overall more like 2nd order, like the rest?)

Well, there's two LC networks to contend with (input L, coupling C, output L, output C) and the RHPZ when in boost mode so it seems true 4th order behavior would be difficult to avoid even with CMC. However, I haven't given it much thought, either, since the one real SEPIC I did design was part of a much larger system so I didn't really have the time to mess around with it. Drastically lowering fc was an expedient, if not exactly elegant/correct, way of solving a stability problem that might or might not have been because of the transfer function.
 

Offline T3sl4co1l

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Re: Low EMI SMPS - How to design to pass FCC
« Reply #9 on: December 08, 2019, 01:32:12 pm »
Hah yep... that was the last one I did for production actually, TPS40210 SEPIC.  Automotive, hence the wide input range.  Not much power, a few watts.  Problem I had is the error amp output saturates above the fault threshold.  So instead of a nice well-behaved current limit, it just fucking shuts down and sits there wheezily burping.

Ended up removing the soft start cap, so it burps fast enough to deliver about half the nominal current.  Enough to get things started for the app.

Stupid chip.


But as for theory vs. reality, a favorite example of mine is the dawning realization in the late 90's that injecting a little bit of the clock ramp into the current sense input of a CMC controller can improve its noise tolerance at light loads and eliminate subharmonic oscillation at heavy loads. Eventually theory worked out the reasons for using so-called slope compensation, but only after the fact, not before it.

Ah, I suppose that figures.  Who cares about theory when it Just Works?  It's just a piddly little power converter, not like it's an airframe with full state vector controls, who cares about analysis... ::)

Tim
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Offline MagicSmoker

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Re: Low EMI SMPS - How to design to pass FCC
« Reply #10 on: December 08, 2019, 01:45:41 pm »
...the error amp output saturates above the fault threshold.  So instead of a nice well-behaved current limit, it just fucking shuts down and sits there wheezily burping...

Oh, that's an even worse cause for instability than I suspected. Welp, it's still on my Do Not Ever Use Again list.


Ah, I suppose that figures.  Who cares about theory when it Just Works?  It's just a piddly little power converter, not like it's an airframe with full state vector controls, who cares about analysis... ::) 

Somebody clearly doesn't work for Boeing...  :P
 

Offline T3sl4co1l

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Re: Low EMI SMPS - How to design to pass FCC
« Reply #11 on: December 08, 2019, 02:33:34 pm »
Ouch  >:D
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Offline SiliconWizard

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Re: Low EMI SMPS - How to design to pass FCC
« Reply #12 on: December 08, 2019, 04:48:02 pm »
Ah, I suppose that figures.  Who cares about theory when it Just Works?

A variation of this can be: who cares about theory when it just passes FCC?  ;D
 


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