Author Topic: Low jitter trigger circuit for a frequency counter  (Read 2447 times)

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Offline TmaxElectronicsTopic starter

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Low jitter trigger circuit for a frequency counter
« on: March 24, 2019, 11:31:19 am »
Hello,

I have a project that will log the mains frequency deviation over time and i need a reliable trigger circuit.

I have already tried to just use a comparator (general purpose and a fast prop. delay one) but i observed about 100us of jitter across one cycle time of the waveform
(yes that is only a fraction of the actual waveform and easily enough for measuring 50Hz but since i want this to be really acurate i would need one that has at most 1us of jitter, with lower of course being better).

What am i doing wrong/which part should i use?

BTW i did google this and try out the first few results but they all had the same issue and i didn't quite know what exactly to google for after that.
« Last Edit: March 24, 2019, 07:02:39 pm by TmaxElectronics »
 

Offline Rerouter

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Re: Low jitter trigger circuit for a frequency counter
« Reply #1 on: March 24, 2019, 11:40:20 am »
If you ever look at mains with a scope, generally it is extremely noisy, your idea for a trigger would likely work if you had an aggressive low pass or band pass filter.

as your only after drift in frequency, measure the zero crossing with some hysteresis, and have a dead time to ignore any secondary pulses.
 

Offline TmaxElectronicsTopic starter

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Re: Low jitter trigger circuit for a frequency counter
« Reply #2 on: March 24, 2019, 12:03:06 pm »
So far i was only running it from my signal generator so there probably wasn't too much noise on the input signal ;) .

And i also had some hysteresis (220k and 47k as the comparator wouldn't sink a lot of current).

I also just tested the setup using other waveforms and it appears that the jitter was always at ~1/500 of the rise time so using a square wave completely eliminated any jitter, not sure if that is in any way important though.
 

Offline RoGeorge

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Re: Low jitter trigger circuit for a frequency counter
« Reply #3 on: March 24, 2019, 01:34:00 pm »
What am i doing wrong

You are looking at each trigger point instead of averaging for a very long number of periods.

Offline Benta

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Re: Low jitter trigger circuit for a frequency counter
« Reply #4 on: March 24, 2019, 01:47:05 pm »
Timebase is the word, not trigger.
Measuring an AC sine wave precisely is close to impossible, the tiniest drift in DC levels will offset the measuring point significantly. This also goes for squaring up the sine wave with a Schmitt trigger, comparator or whatever.
Your best bet is averaging as RoGeorge says.
 

Offline Kleinstein

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Re: Low jitter trigger circuit for a frequency counter
« Reply #5 on: March 24, 2019, 01:58:13 pm »
Mains frequency is relatively low and the "sine" wave is full of distortion. So it is essentially impossible to get a simple accurate trigger on something like the zero crossing. Due to the low frequency the method of choice would be more like some filtering and than digitize the waveform and fit a sine wave to it. If done in a clever way the computational demand is not that large and even a simple µC could do that job quite well.

If it really has to be trigger like, it would be more filtering (to get rid of most of the harmonics) and than triggering an every zero crossing and include them all in the calculation. The actual triggering (e.g. comparator with some hysteresis) would not be that critical, as the input signal is jittery anyway.
 

Online nctnico

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Re: Low jitter trigger circuit for a frequency counter
« Reply #6 on: March 24, 2019, 02:07:25 pm »
Timebase is the word, not trigger.
Measuring an AC sine wave precisely is close to impossible, the tiniest drift in DC levels will offset the measuring point significantly. This also goes for squaring up the sine wave with a Schmitt trigger, comparator or whatever.
Your best bet is averaging as RoGeorge says.
There are ways to do this.
This board uses a 10MHz sine wave which then gets shaped and filtered (schematics are also available from this page). This is more like metrology grade stuff but a similar approach is probably useful for the OP.
https://www.ohwr.org/project/wrs-low-jitter/wikis/home
There are small lies, big lies and then there is what is on the screen of your oscilloscope.
 

Offline Benta

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Re: Low jitter trigger circuit for a frequency counter
« Reply #7 on: March 24, 2019, 02:25:36 pm »

There are ways to do this.
This board uses a 10MHz sine wave which then gets shaped and filtered (schematics are also available from this page). This is more like metrology grade stuff but a similar approach is probably useful for the OP.
https://www.ohwr.org/project/wrs-low-jitter/wikis/home

Hell of a difference between an nice clean 10 MHz signal and dirty 50 Hz mains.
 

Offline TmaxElectronicsTopic starter

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Re: Low jitter trigger circuit for a frequency counter
« Reply #8 on: March 24, 2019, 02:31:45 pm »
thanks guys,

i was able to get the jitter down to about +-5us with a diode clamped input and lots of filtering, i was just hoping to get away with as little averaging as possible.

Measuring an AC sine wave precisely is close to impossible, the tiniest drift in DC levels will offset the measuring point significantly.

But any offset would cancel itself out, as i am only interested in the period, so a short on-time would be offset by the larger off-time, right?
 

Offline Kleinstein

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Re: Low jitter trigger circuit for a frequency counter
« Reply #9 on: March 24, 2019, 03:11:03 pm »
An DC offset, if not too large would mainly change the On/off ratio. So it would not be a big problem. The bigger problem is more like higher harmonics and their variations, as they can move the zero crossing. Something lime switched mode power supplies can be such nonlinear loads that can cause such waveform distortions.

For a longer time to measure the frequency there are different ways of "averaging". Depending on the type of noise, different methods to calculate the frequency are best. With noise due to white phase noise, like jitter from a poor trigger, a good way would be a kind of linear interpolation of zero crossing time versus count number. If the trigger is perfect and noise is more like a poor oscillator the better method would be just looking at the 1 st and last time in the interval.

With the mains frequency it's more like the trigger noise case, though there are true variations in the frequency too.
 

Online nctnico

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Re: Low jitter trigger circuit for a frequency counter
« Reply #10 on: March 24, 2019, 03:25:23 pm »

There are ways to do this.
This board uses a 10MHz sine wave which then gets shaped and filtered (schematics are also available from this page). This is more like metrology grade stuff but a similar approach is probably useful for the OP.
https://www.ohwr.org/project/wrs-low-jitter/wikis/home

Hell of a difference between an nice clean 10 MHz signal and dirty 50 Hz mains.
At the ps level there is no such thing as a clean 10MHz signal. That is why I wrote: the problems are similar albeit at a different time scale.
There are small lies, big lies and then there is what is on the screen of your oscilloscope.
 

Offline TmaxElectronicsTopic starter

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Re: Low jitter trigger circuit for a frequency counter
« Reply #11 on: March 24, 2019, 07:02:14 pm »
i now got it to work.

I used a circuit similar to the one of the 100MHz thing, but with more filtering and some aggressive hysteresis on the comparator (using a capacitor across the resistor between the output and input) and applied a really long term average that takes into account each sample taken. In terms of stability i can get to x.0001Hz accuracy with just the least significant digit jumping about (obviously from my signal generator - when using the actual mains it moves up and down by ~0.03 Hz periodically). And the accuracy seems to be fine too (at 500kHz without the filter it measures 500950Hz - 501050Hz).

Thanks again  :-+
 

Offline David Hess

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Re: Low jitter trigger circuit for a frequency counter
« Reply #12 on: March 24, 2019, 08:22:43 pm »
The problem is basing the measurement off of a single point in the noisy input waveform.  Instead, an integrated measurement over all or part of the waveform is necessary so noise has less of an effect.

1. Filter the input to the desired measurement bandwidth including low and high pass.  If preservation of phase is important, then take this into account.  Notch out the lower harmonics.
2. Phase lock a sine oscillator to the filtered power line signal using an integrating phase detector like an analog multiplier.
3. Measure the now cleaned signal using the trigger circuit of your choice.

It would be interesting to frequency multiply the cleaned signal to drive a switched capacitor filter for the noisy input signal so the filter tracks the input but I doubt this is necessary for most applications.

Building a 50 or 60 Hz low noise voltage controlled oscillator is an interesting challenge in itself but there are a couple of ways to do it also using analog multipliers.

 

Offline Kleinstein

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Re: Low jitter trigger circuit for a frequency counter
« Reply #13 on: March 25, 2019, 05:11:19 pm »
With only 50/60 Hz and the rather high amount of noise, there is no more need to do all the filtering analog. Digital filtering or a kind of digital PLL based on digitized data are probably easier.
 

Offline David Hess

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Re: Low jitter trigger circuit for a frequency counter
« Reply #14 on: March 26, 2019, 01:41:28 am »
With only 50/60 Hz and the rather high amount of noise, there is no more need to do all the filtering analog. Digital filtering or a kind of digital PLL based on digitized data are probably easier.

I agree but the analog design gives a map of the minimum requirements in a digital implementation.  I would still implement some low and high pass filtering before the ADC.
 


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