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Low jitter trigger circuit for a frequency counter
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nctnico:

--- Quote from: Benta on March 24, 2019, 02:25:36 pm ---
--- Quote from: nctnico on March 24, 2019, 02:07:25 pm ---
There are ways to do this.
This board uses a 10MHz sine wave which then gets shaped and filtered (schematics are also available from this page). This is more like metrology grade stuff but a similar approach is probably useful for the OP.
https://www.ohwr.org/project/wrs-low-jitter/wikis/home

--- End quote ---

Hell of a difference between an nice clean 10 MHz signal and dirty 50 Hz mains.

--- End quote ---
At the ps level there is no such thing as a clean 10MHz signal. That is why I wrote: the problems are similar albeit at a different time scale.
TmaxElectronics:
i now got it to work.

I used a circuit similar to the one of the 100MHz thing, but with more filtering and some aggressive hysteresis on the comparator (using a capacitor across the resistor between the output and input) and applied a really long term average that takes into account each sample taken. In terms of stability i can get to x.0001Hz accuracy with just the least significant digit jumping about (obviously from my signal generator - when using the actual mains it moves up and down by ~0.03 Hz periodically). And the accuracy seems to be fine too (at 500kHz without the filter it measures 500950Hz - 501050Hz).

Thanks again  :-+
David Hess:
The problem is basing the measurement off of a single point in the noisy input waveform.  Instead, an integrated measurement over all or part of the waveform is necessary so noise has less of an effect.

1. Filter the input to the desired measurement bandwidth including low and high pass.  If preservation of phase is important, then take this into account.  Notch out the lower harmonics.
2. Phase lock a sine oscillator to the filtered power line signal using an integrating phase detector like an analog multiplier.
3. Measure the now cleaned signal using the trigger circuit of your choice.

It would be interesting to frequency multiply the cleaned signal to drive a switched capacitor filter for the noisy input signal so the filter tracks the input but I doubt this is necessary for most applications.

Building a 50 or 60 Hz low noise voltage controlled oscillator is an interesting challenge in itself but there are a couple of ways to do it also using analog multipliers.

Kleinstein:
With only 50/60 Hz and the rather high amount of noise, there is no more need to do all the filtering analog. Digital filtering or a kind of digital PLL based on digitized data are probably easier.
David Hess:

--- Quote from: Kleinstein on March 25, 2019, 05:11:19 pm ---With only 50/60 Hz and the rather high amount of noise, there is no more need to do all the filtering analog. Digital filtering or a kind of digital PLL based on digitized data are probably easier.
--- End quote ---

I agree but the analog design gives a map of the minimum requirements in a digital implementation.  I would still implement some low and high pass filtering before the ADC.
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