Low noise 0.01Hz-1+MHz amplifier project

[CurtisSeizert]

I have been working on a low noise preamplifier that is suitable for characterizing very low level signals riding on a significant DC bias voltage. I am planning on putting the KiCAD project files up on Github, and I'll post a link to the repo when I do. I have primarily used it for characterizing noise of voltage references, but it should be applicable to various other low-level AC amplification tasks. The input stage uses a 23uF/100M HP filter (Fc = 69 uHz) and a composite amplifier made from 16 paralleled JFE2140s and an OPA140 operating at a fixed gain of 501. The tail current of each JFET pair is 800 uA, and the differential amplifier input stage uses a cascode + inverted cascode topology. Active biasing of the inverted cascode ensures that the OPA140 inputs stay close to ground. This input stage gives a wideband noise density of about 0.62 nV/rtHz with a 1/f corner of a few Hz. Noise from 0.1-10Hz is 2.78 nVRMS (16.7 nV p-p), and noise from 0.01-10 Hz is 3.18 nVRMS (19.1 nV p-p).

The unit is powered by 4x21700 Li-ion cells on a separate board with a BMS for balanced charging, etc., as well as an integrated charger based on the BQ24618 to give a full charge in about 2.5 h. The current draw with shorted inputs is ~30mA, so battery life is >100h. The enclosure is a Hammond 1457N1601 (~160x100x50 mm) with PCBs for the front and rear panels (the battery charger is on the inside of the rear panel).

A few other points about the design:
-The basic signal train is: Input HP filter -> A1, G=501 -> HP filter -> Gain stage (G=20/200) -> HP filter -> Buffer -> LP Filters -> SW -> Output
-Input capacitance is about 100 pF (though see point below), which is primarily from the PCB itself. This will be reduced in a future revision.
-A series 330R + 470pF from input to ground was required to damp out oscillations with certain op-amp buffered inputs. This will be connected via relay in a future revision, but increasing the impedance of the feedback network for the input stage should help as well.
-There are three bandwidth options for LP filtering  - wideband goes to about 2.5 MHz (-3dB), and there are two fourth-order Butterworth filters in Sallen-Key topology for low pass filtering to 10 kHz and 10 Hz.
-There are two HP filter cutoff points, 0.01 and 0.1 Hz, as well as a "settle" mode which shorts the output of both HP filters to GND with MMBF4117 JFETs.
-Gain is switchable (60, 80, and 100 dB). The 100 dB gain setting has limited utility because signals and amplified at full bandwidth prior to the LP filters, so it saturates easily. I will add some pre-filtering in a future revision to improve dynamic range for such cases. The 60dB gain setting uses a 9k/1k divider prior to the first (non-input) HP filter.
-There are window comparators to detect saturation before both HP filters. These trigger 555 timers that drive warning LEDs on the front panel.
-The capacitors for the input HP filter are a pair of Kemet C4AQLLW5120A34K polypropylene capacitors. These had the best leakage and DA of the suitably low-profile capacitors I tested, and I don't believe selection will be required for bias voltages of 25V or less, but they are definitely not specified for the >2TOhm parallel resistance I observed in the samples I tested.

I have attached some photos of the project and a pdf of the schematic for the amplifier board.

Edit: Here's the link to the github repo: https://github.com/curtisseizert/LowFreqLNA/tree/main

[CurtisSeizert]

More photos due to the size limit.

[CurtisSeizert]

Also, here are a few VSD plots at 0.01-10Hz bandwidth for the amplifier itself and some a voltage reference. These were captured with a 3458a sampling at 50 SPS. I think all used 1.5M samples.

[moffy]

An excellent low noise amplifier, particularly impressive is the 1/f performance. That is a laboratory grade instrument, and having recently dabbled with some low noise circuits requires a lot of attention to detail. Kudos also for making it public.

[TimFox]

Nice work, especially for low "excess", "pink", or "1/f" noise.
Could you regraph the data with a log scale for the noise voltage density?

[jbb]

Oooh, that's a lot of JFETs 
And some very nice curves!

I have a question about the innards of the input amplifier.

My assumptions:

• There's a JFET diff pair and cascode stage (Q26) which looks very sensible
• Q27 is a current mirror, which - I think?? - is normally used for converting a the differential current from the cascode into a single-ended output current
• Then there's a cascode stage using Q28 to get those currents into R70, R73.
• U13A and Q29 seem to be a servo for controlling Q28.1, Q28.2 biasing...
• R70, R73 convert JEFT amplifier currents into voltages for handoff to U14

The Q26 cascode input biasing looks interesting.  Is it done that way to help with input common mode rejection?

Does that servo with U13A behave nicely? Does it tend to peg at full rail and rely on the "100k bodged in at source of Q29"? Does it tend to split the current into R70 and R73?

I was thinking that a simpler option might be to replace Q27, Q28, U13A with a folded cascode (as is apparently common in CMOS opamps)?. Never mind: realised that R70, R73 would need to be a lot smaller (e.g. 1k) to handle the bias current.

[CurtisSeizert]

Thanks both for the kind words.

Here are some more VSD plots and some previous ones replotted on log/log scales. I did not bother replotting the 6k04 J-N Noise calibration plot because it is flat. The new ones were digitized on an Analog Discovery Pro. The first two show noise and frequency response for inputs grounded through 0R and 6k04, respectively. I cut the graph off on the left at 1 kHz for the sake of getting a smoother curve. The third plot is the noise floor with the 10kHz LP filter on log/log axes to show the 1/f corner. It seems to be a bit higher frequency than I have seen it in the past, which may be from the frontend of the ADP3450. The fourth is the noise floor from 0.01-10Hz on log/log axes, and the final one is a handful of ADR1000-based 10V references. I don't know why the green trace has such a low flicker noise slope, but I have run it twice to confirm.

This amplifier is actually a fair bit worse for 1/f noise than a previous revision with an identical input stage. I suspect it is from the JFETs on this one being salvaged from previous prototypes, since I used new ones for that version. I can't find the capture I took to plot the VSD for the previous version, so I'll have to put it back together and run it for posterity.

The wideband VSD plot is indicative of the frequency response I saw during testing using the network analyzer function of the ADP3450. The response showed 0.1 dB flatness to ~250 kHz and a -3 dB point of 2.5 MHz with no gain peaking.

[David Hess]

When I originally saw the title, I thought I was going to suggest checking out the design of the Tektronix 7A22, but you have things well in hand.

With a differential input stage, why not make the input fully differential?  Then external common mode noise could be rejected also, although it would require a different scheme for AC coupling, probably including bootstrapping.

[CurtisSeizert]

I'll save you the trouble of building the LTSpice schematic - I have attached it. I measured the parasitic capacitance from various nodes to GND and added those as well. Note that you'll need to either download the TI models and change the names (they use things like OPAx140, etc., which mildly annoys me, so I change the .lib files) or try a similar ADI part. I think the ADA4622 would be closest for the OPA140, or perhaps the ADA4627. There are a pair of antiparallel diodes across the op amp inputs in the LTSpice model to get it to behave better. This model very accurately reproduces the behavior of the actual circuit.

The diff pair JFETs are run at a drain-source voltage of about 1.2V (enforced by the cascode) to minimize gate leakage and power dissipation in the JFETs. Minimizing power dissipation is crucial to avoid thermal gradients that can masquerade as 1/f noise. The loads for each leg are formed by the emitter-degenerated current mirror (Q27). This gives reasonably high impedance with moderate voltage drop. The inverted cascode (Q28) keeps the outputs from the diff pair within the common mode range for the op amp. JFET input op amps require a fair bit of headroom from the positive rail for their inputs. The OPA140 requires 3.5V, and 2.5V-3.5V headroom is very common. Omitting the inverted cascode would really restrict the choice of op amps for the input stage. U13A is indeed a servo for biasing the inverted cascode. The 100k source resistor I bodged in to connect Q29 to the positive rail is to reduce the gain of the servo to keep it from oscillating with certain inputs. I have simulated versions where the cascode Q26 is omitted because I would have preferred to leave it out, but it is necessary to maintain phase margin, especially with inductive-seeming inputs (including certain configurations of OPA2205, which I really like).

The servo isn't really necessary for CMRR - the cascode Q26 would be sufficient for that. I am sure it doesn't hurt, but CMRR isn't really too big a concern when operating at such high gains. The input common mode range for the input stage is only about +/- 8 mV. One thing I failed to realize when I initially designed this is how important the impedance of the feedback network is. At the point where the loop gain of the hybrid amplifier reaches 0 dB, the output impedance of the OPA140 is non-zero and rising. This is probably more important for stability than f_t of the feedback leg of the JFET pairs (based on some napkin math, it should be about 63 MHz at this tail current). So at a high enough impedance of the feedback network, the large input capacitance of the 16 paralleled JFETs would form a pole with the feedback network, which would degrade phase margin, leading to instability. With a 2k49 || 15 pF - 4R99 divider, the phase margin is comfortably above 60 degrees, even with some moderately inductive inputs.

The most challenging aspect of designing this was not the noise, it was making sure it wouldn't oscillate. Also the layout of all those JFETs was a PITA. Thanks for noticing the servo. I thought it was a clever little trick.

[CurtisSeizert]

David - I had considered that, and I may in the future, but I was at a point with this project where it needed to be usable without a redesign of the input stage. Common mode noise is definitely one of the more problematic things when using the current design, and I have resorted to using batteries to power DUTs if I want to keep noise to a minimum.

[David Hess]

Common mode noise is definitely one of the more problematic things when using the current design, and I have resorted to using batteries to power DUTs if I want to keep noise to a minimum.

I have done the same thing and also directly connected the DUT to the amplifier input without a cable.

In practice when comparing single ended designs, which should have a 3dB advantage in noise, to differential designs, the common mode rejection of a differential design makes more than a 3dB difference when typical probe connections were used.

One problem with a differential input design is how to handle AC coupling.  If AC coupling is used at the inputs, then where the low frequency transition band does not match, common mode noise will be converted into a differential mode signal.  Tektronix's solution for this was to DC couple the inputs and apply a precision DC reference to one input.

One method I have used is to use DC coupling at the inputs and then apply AC coupling at the differential to single ended conversion stage with a servo amplifier.  I am not sure why Tektronix did not do it this way.  Either method requires the inputs to have a common mode range which includes the DC component of the signal, which will mean bootstrapping the input amplifier adding even more complexity.  The 7A13 achieved a +/-10 volt input range this way, and the 7A22 managed +/-1 volts, which does not seem impressive but that was at 10 microvolts/division or an amplification of 100,000.  Typical oscilloscope inputs back then had a common mode range of perhaps +/-100 millivolts.

[CurtisSeizert]

David - thanks for getting me to think about this again. It may be possible to adapt the input stage to have differential inputs without too much hassle. I simulated a possible scheme in LTSpice, which I attached. The AC coupling caps are small for ease of simulation. This would require the sources of the JFETs on each leg to be paralleled, but that should be feasible with the JFE2140. I have found parts from the same order to have low Vgs spreads (~30 mV for 20 parts) at the drain currents that I have tested. In this amplifier, integrator U4 modulates the base voltage of loads Q8 and Q7 to keep the output common mode voltage near the source voltage of the input diff pair. This reduces dissipation in feedback resistors R5 and R6 and helps CM rejection at low frequency. Some tweaking can probably improve this further. The differential outputs can be fed into a subtractor and HP filtered as a single ended signal. Also, this should have similar noise as the single ended version.

I will need to try some things and do a more thorough stability analysis before laying out the board. I may even be able to fit it in the same box.

[magic]

Wouldn't a bipolar opamp work just as well in place of OPA140, without all the superfluous complexity?

The usual reason for shunning BJT is their base current and noise, but I think contribution of a relatively low current IC input stage would be negligible compared to all the noise you are already adding with bipolar cascodes and current mirrors conducting full JFET current.

Regarding input pair load impedance, it only needs to be high enough to overcome voltage noise of the integrator opamp. A few volts dropped across ordinary passive resistors might be enough if the opamp is a quiet one, and again, going bipolar could help.


That's my $0.02. You have built a fairly impressive beast, nevertheless.


edit
YMMV, but I have downloaded your sim, replaced OPA140 with LT1007 and simply removed the mirror. V(onoise) is almost right on top of V(j1)+V(j2)+V(r6).

edit edit
But bandwidth is reduced for some reason. Also, I realized that the input stage is still effectively loaded by 10kΩ rather than merely 330Ω due to the folded cascode. And removing the latter broke the simulation for some reason, I have no time to investigate right now.

[David Hess]

David - thanks for getting me to think about this again. It may be possible to adapt the input stage to have differential inputs without too much hassle. I simulated a possible scheme in LTSpice, which I attached. The AC coupling caps are small for ease of simulation. This would require the sources of the JFETs on each leg to be paralleled, but that should be feasible with the JFE2140. I have found parts from the same order to have low Vgs spreads (~30 mV for 20 parts) at the drain currents that I have tested. In this amplifier, integrator U4 modulates the base voltage of loads Q8 and Q7 to keep the output common mode voltage near the source voltage of the input diff pair. This reduces dissipation in feedback resistors R5 and R6 and helps CM rejection at low frequency. Some tweaking can probably improve this further. The differential outputs can be fed into a subtractor and HP filtered as a single ended signal.

Take a look at how the Tektronix AM502 differential amplifier works, as well as true instrumentation amplifiers, as opposed to the "3 operational amplifier" type instrumentation amplifiers which essentially have two differential pairs in series further increasing noise.  The Tektronix 7A13 and 7A22 are less relevant because they have differential outputs and never do the differential to single ended conversion, but the AM502 does.

Also, this should have similar noise as the single ended version.

My comment about noise compared single ended to differential designs.  Yours is a differential design with a single ended input which is also sometimes used in oscilloscopes for I think balance reasons.  (1) Yours should have identical noise to a fully differential design even though it only has one input.

Wouldn't a bipolar opamp work just as well in place of OPA140, without all the superfluous complexity?

The usual reason for shunning BJT is their base current and noise, but I think contribution of a relatively low current IC input stage would be negligible compared to all the noise you are already adding with bipolar cascodes and current mirrors conducting full JFET current.

...

But bandwidth is reduced for some reason. Also, I realized that the input stage is still effectively loaded by 10kΩ rather than merely 330Ω due to the folded cascode. And removing the latter broke the simulation for some reason, I have no time to investigate right now.

The source impedance at the OPA140 inputs is 10 kilohms, so an LT1007 is not optimal, and bipolar parts which are optimal like the LT1001 or LT1012 are much slower, and even the LT1007 is not that fast.  Of course the load resistors for the cascode could be lowered in value, but the OPA140 is pretty low noise, better than an LT1012 and competitive with an LT1007 except at low frequencies, and the JFET input gives a nice boost to bandwidth and slew rate.

Why use a folded cascode at all, especially in an AC coupled design?  The supply voltages are pretty low and the best operational amplifiers do not have rail-to-rail inputs.

(1) The Tektronix 475 or 475A or both do this, but I am not sure why.  It might have something to do with hybrid construction.  Oscilloscopes usually do it to support an offset input, but the 475/475A lack that.

[magic]

The only thing that matters is current noise divided by transconductance of the JFETs, and voltage noise divided by 10kΩ and further divided by transconductance of the JFETs. If you want to be pedantic, selection for 10kΩ source impedance is wrong too because the optimal value of 10kΩ is infinity so it should be corrected and then an opamp selected for that.

But, thankfully, integrator noise is not something that needs to be optimized, it's something that only needs to be good enough. LT1007 is good enough. Why LT1007? Because it's one of the first things that pop up in LTspice that's good enough. I downloaded TI OPA210 model and it simulates just as well as LT1007, while having twice the GBW of OPA140. And wider CMIR.

I don't think that OP is tied to JFET opamps. Particularly if there is already a bunch of BJTs in the same circuit, happily pumping their base current noise into the same JFETs.

[magic]

A more serious attempt at simplifying the input stage attached.

My motivation is not just obsession with minimalism, although that too, but also a practical concern about base current noise of all those discrete transistors. Your measurements still indicate a few dB of flicker noise not accounted for by simulation, and besides thermal effects and maybe excess noise of resistors, these transistors are among chief suspects in my opinion.

This opinion is backed by simulation experiments, where high current noise opamps like LT1028, AD797 or OPA211 notably increased simulated flicker noise of this amplifier, unlike OP140. Given that some of the discrete transistors operate at an order of magnitude higher base current, even if they are less "1/f noise prone" than the monolithic transistors, perhaps due to larger geometry, I think it's not unreasonable that they could be contributing meaningfully to overall input referred noise of the amplifier.


The folded cascode is removed easily by switching to an IC with higher common mode input range. Old OPA2134 simulated OK, despite higher flicker noise. Removal of the 10kΩ resistors increases voltage gain of the differential pair, which gain greatly reduces harm from the integrator's voltage noise. Numerous bipolar parts also simulated well, such as LT1468. Perhaps even NE5534, but I have no models of its low frequency current noise.

The current mirror is a more interesting target for elimination, because it operates at much higher current. Unfortunately, this means giving up a lot of voltage gain, raising sensitivity to voltage noise. I don't think there currently exists a single FET opamp suitable for such job, but OP27 types and OPA210 appear workable. Among those, OP37/LT1037 are the fastest that came to my mind. Removal of the mirror permits increase of load resistors from 330Ω to 470Ω.

edit: Actually, plugging OP140 into the circuit below (with dedicated higher supply voltage) gives only mild flicker noise deterioration, still better than real world measurements of your build. So not sure why I believed otherwise, but modern JFET opamps could be marginally viable noise-wise without current mirror. But CMIR is an issue.

This leaves us with the first cascode, which you want to include for inductive source stability. I'm out of ideas now; its noise could be reduced by darlingtonization (also the current mirror's, by the way) but this eats into the available voltage headroom, precluding the use of OP37. So this is it for now.


Regarding plots below,
- green is the overall input referred noise
- blue is the contribution of parts that can't reasonably be removed
- red shows the shape of overall closed loop signal gain

[David Hess]

This opinion is backed by simulation experiments, where high current noise opamps like LT1028, AD797 or OPA211 notably increased simulated flicker noise of this amplifier, unlike OP140. Given that some of the discrete transistors operate at an order of magnitude higher base current, even if they are less "1/f noise prone" than the monolithic transistors, perhaps due to larger geometry, I think it's not unreasonable that they could be contributing meaningfully to overall input referred noise of the amplifier.

Broadband noise depends on the base spreading resistance which depends on the transistor's construction and layout.  Integrated transistors can have absurdly low base spreading resistance and associated noise and this was a feature of parts like the LM395 and MAT series.  Discrete transistors like the Zetex (now Diode Incorporated) Super E-Line also have very low base spreading resistance and therefor low noise.  There is not much information on it, but I suspect ring and perforated emitter transistors also have low base spreading resistance.

Transistors with low base spreading resistance and therefor low noise have higher 1/f noise corners but this is because their broadband noise is lower and not because of higher flicker noise.  Beyond processing and surface effects, I do not know what contributes to flicker noise.  My guess is that low base spreading resistance also leads to lower levels of flicker noise.

http://www.dicks-website.eu/low_noise_amp_part3/part3.html

The current mirror is a more interesting target for elimination, because it operates at much higher current. Unfortunately, this means giving up a lot of voltage gain, raising sensitivity to voltage noise. I don't think there currently exists a single FET opamp suitable for such job, but OP27 types and OPA210 appear workable. Among those, OP37/LT1037 are the fastest that came to my mind. Removal of the mirror permits increase of load resistors from 330Ω to 470Ω.

Just thinking out loud, but why have load resistances at all?  Why not drive the VAS directly, at the inverting input, from the output of the current mirror?  Then the operational amplifier's common mode voltage can be fixed at a convenient level.

This leaves us with the first cascode, which you want to include for inductive source stability. I'm out of ideas now; its noise could be reduced by darlingtonization (also the current mirror's, by the way) but this eats into the available voltage headroom, precluding the use of OP37. So this is it for now.

The first cascode also controls the drain voltage which has advantages.

Does the first cascode, or current mirror, contribute significant noise anyway?

[MiDi]

Also, here are a few VSD plots at 0.01-10Hz bandwidth for the amplifier itself and some a voltage reference. These were captured with a 3458a sampling at 50 SPS. I think all used 1.5M samples.

What a nice project!

How was the 3458A configured?
Did something similar for an ULF-ULNA prototype - spoiler attached

[magic]

My guess is that low base spreading resistance also leads to lower levels of flicker noise.

I'm sure it reduces conversion of base current noise into base-emitter voltage noise.
Where exactly the 1/f base current noise itself comes from, I frankly don't know.

http://www.dicks-website.eu/low_noise_amp_part3/part3.html

This is poor measurement technique, because it passes base current noise through a mere 100μF. Horowitz&Hill used many mF in analogous tests.

You would expect this ideal transistor below to have flat noise over frequency, but not if you treat it like that. Similarly, a real transistor with 1/f current noise will appear to have 1/f² voltage noise in that setup, and you can see steeper than 1/f slopes in a few specimens there.

Just thinking out loud, but why have load resistances at all?  Why not drive the VAS directly, at the inverting input, from the output of the current mirror?  Then the operational amplifier's common mode voltage can be fixed at a convenient level.

Does the first cascode, or current mirror, contribute significant noise anyway?

You would have to ask Toshiba if it's significant, I don't have the numbers for these transistors.

Sticking to the "Vbe voltage noise" plus "Ib current noise" model, both contribute noise to current mirrors. Vbe voltage noise can be suppressed by degeneration, but Ib current noise simply flows into one or another branch of the differential amplifier, completely uncontrolled. Ditto for cascodes. Ultimate effect is exactly the same as with base current of an opamp connected to the same node, so my logic is simply that these transistors running at 6mA collector current are unlikely to be much more benign that some AD797 or such.

Using bipolar current mirror followed by a JFET opamp "to avoid bipolar current noise" is plain and simple cheating. You are dealing with bipolars either way, you have current noise either way, might as well acknowledge this fact and select rationally the least evil bipolar solution.

That being said, replacing a current mirror with resistors opens another can of worms, which is resistor excess noise. Unfortunately, I'm not familiar with real world magnitude of that effect, if somebody thinks I'm barking at the wrong tree please correct me. Maybe reducing mirror degeneration would be more productive, for example.

[Kleinstein]

The input current noise is not just the current noise originating from the input transistor. There is also noise in the current source at the differential stage.

Normally the noise of the cacode and current mirror transistors is not that relevant - it is often more the resistors at the current mirror that can be relevant and as it is about current noise larger resistors are better. The 330 Ohm resistors have more noise than most BJTs operated at some 6 mA.

For the resistor excess noise it depends on the resistor type. Some are more noisy than others and the datasheets may not give much help as the values given may well be test limits and for the whole resistance range. Usually wire wound are considered nearly noise free and thin film type better than thick film, though it really depends. E.g. I found noticable (~-35 dB noise index) excess noise for PTF56 type thin film THT resistors not better than some thick film ones I had at hand. One the other end for Susumu RR type SMD ones I could not detect excess noise with my setup ( < -50dB noise index). Even the PTF56 resistors are likely OK: maybe comparable 1/f noise to the BJTs but likely less than the JFETs.

[TimFox]

Note that the relevant noise terms are "noise current and noise voltage referred to the input".
The physical noise generators are all over the circuit, but using the gain from the input node to the actual generators allows them to be referred to the input for useful calculations.

[magic]

Does the first cascode, or current mirror, contribute significant noise anyway?

You would have to ask Toshiba if it's significant, I don't have the numbers for these transistors.

Actually, Toshiba gives certain numbers.

At 10Hz, HN4A51J datasheet shows 12dB noise figure at 6mA for circa 1800Ω source impedance.
Johnson is 5.4nV/rtHz and 12dB more is 21.6nV.
Subtracting Johnson, 21nV/rtHz is left. Voltage noise of the transistor is negligible, sub-1nV.
Dividing 21nV by 1800Ω (ignoring base spreading resistance) gives ~11pA/rtHz.

Repeating the calculation for 1kHz yields 2.2pA/rtHz, and this is consistent with expected shot noise of 15μA base current.
So 10Hz is well below the 1/f corner, and 0.01Hz is likely to be almost 32x more: 0.35nA/rtHz.

For the NPN we get 3000Ω, 9pA/rtHz at 10Hz and estimated 0.3nA/rtHz at 0.01Hz.
Total noise from both pairs is 0.65nA/rtHz. Dividing by 80mS transconductance of the diff pair gives 8.1nV/rtHz equivalent input noise voltage.

This is more than contribution of the JFETs at 0.01Hz (per the datasheet and SPICE model).
It's a pessimistic estimate, assuming exactly 1/f distribution below 10Hz. Perhaps real world is slightly better, but maybe not much better.


Or did I screw up the calculations?
I believe I originally got this procedure from The Art of Electronics, and it sounds sensible. I mean, the part about converting NF plots to i_n and e_n; the extrapolation to 0.01Hz is a separate matter.

[Kleinstein]

The calculations sounds OK, though maybe the extrapolation to 0.01 Hz being a bit tricky with the JFETs.
The choice of the BJTs does not look that good. The HN4A51 and HN4C51 are not really made for that much current. Noise wise they are best used with more like 0.1 to 0.5 mA, especially for low frequencies.

[David Hess]

My guess is that low base spreading resistance also leads to lower levels of flicker noise.

I'm sure it reduces conversion of base current noise into base-emitter voltage noise.
Where exactly the 1/f base current noise itself comes from, I frankly don't know.

I know where the voltage part comes from.  Carriers get trapped in defects causing Vbe to shift, much like the source of popcorn noise, however each defect contributes a very small jump in Vbe for a variable time.  Adding up all of the variable times yields the 1/f voltage noise curve.

Something similar must be happening to generate the 1/f current noise, maybe having to do with the potential the electrons must jump, like with shot noise?

Popcorn noise comes from a single major defect trapping charge causing a large jump, or sometimes a very small number of large defects, and seems to be associated with surface (or interface?) defects.  Surface defects can be traced back to improper processing or contamination.

The above at least is my understanding as there are few available sources on the subject of flicker noise in transistors.  The voltage noise, current noise, and the effects of base spreading resistance are much better described.

http://www.dicks-website.eu/low_noise_amp_part3/part3.html

This is poor measurement technique, because it passes base current noise through a mere 100μF. Horowitz&Hill used many mF in analogous tests.

You would expect this ideal transistor below to have flat noise over frequency, but not if you treat it like that. Similarly, a real transistor with 1/f current noise will appear to have 1/f² voltage noise in that setup, and you can see steeper than 1/f slopes in a few specimens there.

I assume the author was interested in audio applications where flicker noise is less of a concern, and he did say he was not interested in flicker noise.

That being said, replacing a current mirror with resistors opens another can of worms, which is resistor excess noise. Unfortunately, I'm not familiar with real world magnitude of that effect, if somebody thinks I'm barking at the wrong tree please correct me. Maybe reducing mirror degeneration would be more productive, for example.

The current mirror resistors are definitely a source, and must be kept low in value, but would not be required if matched transistors were used.

[TimFox]

Actually, "flicker noise" (pink noise or 1/f noise) is more important at lower frequencies, often below 100 Hz in the audio band.