Electronics > Projects, Designs, and Technical Stuff
Lowest cost way to capture 110 channels of ADC data
teksturi:
--- Quote from: ali_asadzadeh on October 24, 2019, 07:11:35 am ---Guys thanks for the TIPS, I think the Idea that use 1 Pin per ADC sound very good, the main problem would be the Clock and MOSI buffers, and also low jitter clock generation, do you suggest any parts for them? also I think I can convince them to use 10G Ethernet, I have done 1G Ethernet before, But not a 10G one.
--- End quote ---
Just split 110 adc board to 4. Then you can design with 1G ethernet. but 30 for each. Then if some are not working you can just mark them broken. Also board cost would be lower.
--- Quote ---the price is my concern, since my profit would come for using lower cost parts :)
--- End quote ---
If you spend too much time to select low cost parts you will lose lot more money. The main factors should be: easy to design, understandable manuals, easy to buy. You will save your time and that should be valuable. I do not think these board's will be manufacture's large count.
SiliconWizard:
Yeah if the price is your "concern" (will you be manufacturing the devices for the customer?), the fact the cost of the FPGA will be negligible compared to your 110 ADCs still holds.
And if you're actually manufacturing them instead of just selling your design, maybe that contractually means that you'll be allowed to reuse your design for other customers? In that case, that would also be a good point justifiying designing a board with less inputs, and making them able to be coupled/networked for more inputs. A lot more flexible, a lot less constraints. (The only constraint, if you need all inputs to be sampled synchronously, will be to provide a sync signal that coupled boards can share. Thus a single board would have a master sync output and a slave sync input...)
And yeah, you could also look for ADCs with more inputs. Can't you find a similar spec'ed ADC with 4 inputs for instance? That will limit the number of parts, and the overall cost.
Scrts:
--- Quote from: teksturi on October 25, 2019, 12:55:47 pm ---Just split 110 adc board to 4. Then you can design with 1G ethernet. but 30 for each. Then if some are not working you can just mark them broken. Also board cost would be lower.
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This.
I was doing the math... 16bit * 600000 samples/sec * 110 channels = 1.056Gbps?
The data alone would saturate Gbps link, without even talking IP/UDP headers and switching processing time. So even if there will be 4 acquisition boards, the switch has to be capable of >1Gbps link to the PC. Most likely 10Gbps switch?
By the way, the PC load getting such fast data input will be enormous. Is it going to process that much of data? CPU will be chocked as well.
RCinFLA:
Sound like you are specifying what chips can do, not customer requirements.
Given 110 channels.
1) Do the 110 channels have to sample synchronously? If so, what is time tolerance, jitter, on simultaneous samples?
2) Dynamic range, number of useable bits (ENOB)
3) Sample rate.
Depending on requirements you might want to look into ultrasound Rx chips that provide multiple channels of relatively high synchronous sample rate with high speed LVDS output interface mux'g multiple channels.
At other extreme, requiring low sample rating, non-synchronous, look for chips with required resolution and greatest number of muxed input channels. If you need synchronous samples you need a common clock and simultaneous control of start of conversion.
To reduce FPGA IO requirements I would look for a parallel output version ADC with similar 600 Ksps sample rate and use FPGA to read parallel outputs at a multiple subsample rate using each ADC parallel output buffer as a holding buffer. With FPGA running a parallel bus input of about 150 MHz you could circularly read each of 110 ADC's within the 600 ksps sample period. You may be limited by the ADC output enable timing and have to have more parallel FPGA buses for smaller group of ADC's to reduce parallel read rate.
NiHaoMike:
--- Quote from: Scrts on October 25, 2019, 02:27:58 pm ---I was doing the math... 16bit * 600000 samples/sec * 110 channels = 1.056Gbps?
The data alone would saturate Gbps link, without even talking IP/UDP headers and switching processing time. So even if there will be 4 acquisition boards, the switch has to be capable of >1Gbps link to the PC. Most likely 10Gbps switch?
By the way, the PC load getting such fast data input will be enormous. Is it going to process that much of data? CPU will be chocked as well.
--- End quote ---
Don't need a switch, just get a NIC with 4 Gigabit ports, I managed to get one for under $15.
As for handling the data, any half decent SSD will save it with ease. Of which, maybe it would make more sense to make a standalone unit that just accepts a SSD for storage? (How difficult is it to implement SATA host on a FPGA?)
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