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Lowest cost way to capture 110 channels of ADC data
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ali_asadzadeh:
Hi,
One of my customers neededd me to design an FPGA board for him to be able to capture 110 ADC channels simultaneously, the ADC is LTC2378-16 and send it over to a PC trough a 1GB Ethernet port in realtime. Also the ADC clokc should have a low jitter clock in the order of 10ps, I have seen fs jitter clock generators, But they are for high frequency sampling like 250MSPS parts, do we have something for low sampling parts? and also the synchronization time between each channel should not be more than 1us.
The sample rate is around 600KSPS for each ADC, so I have calculated that I needed an FPGA with more than 1200 IO lines, so they are very pricey! Do you have any idea so it can use lower cost Spartan6 or ARTIX series in the 484 pin package, since I have very good prices for them In china, the problem would be to sync the Separate FPGA's and pack all the data in one of them and send it to the PC,

Any Hints or Ideas are highly appreciated!
Marco:
That's the full throughput of 1 Gbps ethernet ... no room for overhead even. That's a bit optimistic.

In theory you only need 1 FPGA input pin per ADC, if you have room for some extra logic ICs to fanout SCK and CNV then those only need 1 pin each on the FPGA.
Miyuki:
I agree, 1 pin per ADC and have some clock "amplifier" to feed all of them
Also if signals are not just noise, data can be reasonable compressed to conserve bandwidth

Most FPGAs have nice clock generating capability from any stable source
It look like a relative simple task even for small one
nctnico:
You can get off-the-shelve data acquisition systems for this purpose.
MagicSmoker:

--- Quote from: nctnico on October 23, 2019, 05:57:03 pm ---You can get off-the-shelve data acquisition systems for this purpose.

--- End quote ---

You can, but the price will make a grown man cry... then again, so will designing this sort of thing yourself.
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