LTspice current injection

[Gaktyt]

Hi,

I made the following simulation in LTspice in an attempt to simulate current injection.

I do not understand why the voltage DC level of the left circuit (with *2 current injected) is equal to the initial capacitor voltage but with opposite sign? Any thoughts on that would be appreciated.

[SiliconWizard]

I've used '.ic' spice directives on LTSpice schematics, but never the individual "IC" parameter for a given component that you seem to be using. I haven't even seen how to set them in LTSpice. What version are you using?

Also, why is B3 dependent on I(C2)?

[Jay_Diddy_B]

Hi,
Please add your .asc file to your post.



When I run this model I get a similar result to what you are reporting.



The reason for this is I rotated C2 180 degrees when I drew the schematic.

If you look at the SPICE netlist you can see this:

Code: [Select]

C1 v_c1 0 1u IC=1
C2 0 v_c2 1u IC=1
R1 v_c1 0 1Meg
R2 v_c2 0 1Meg
.tran 3 uic
* Intial Conditions
.backanno

The IC has a sign, it assumes that the first node is the positive node.

C1 node_1 node_2 1u IC=1

Means node_1 is 1V with respect to node_2

It is the same for currents.

Regards,
Jay_Diddy_B

[SiliconWizard]

Hi,
Please add your .asc file to your post.

(Attachment Link)

When I run this model I get a similar result to what you are reporting.

(Attachment Link)

The reason for this is I rotated C2 180 degrees when I drew the schematic.

If you look at the SPICE netlist you can see this:

Code: [Select]

C1 v_c1 0 1u IC=1
C2 0 v_c2 1u IC=1
R1 v_c1 0 1Meg
R2 v_c2 0 1Meg
.tran 3 uic
* Intial Conditions
.backanno

The IC has a sign, it assumes that the first node is the positive node.

C1 node_1 node_2 1u IC=1

Means node_1 is 1V with respect to node_2

It is the same for currents.

Regards,
Jay_Diddy_B

I didn't know about this IC parameter and never used it.

But given what it does, I think that's one more reason to stick to .ic directives.

You'd add the following on the schematic instead:

Code: [Select]

.ic V(v_c1)=1 V(V_c2)=1

Unambiguous and doesn't rely on any particular orientation of the parts (which I think is nasty.)

[engrguy42]

Yeah, if you CTRL-RT CLICK on a capacitor, for example, you can set initial conditions by doing a "IC=0" on the SpiceLine. But it sucks that you have to do that. Who the hell thought that one up? They should all default to zero. Geesh. That messed me up just the other day doing a time controlled switch closing into a capacitor.

[Gaktyt]

What version are you using?

XVII(x64)

Also, why is B3 dependent on I(C2)?

Because otherwise I can not get it to converge, I guess due to the infinite feedback it would create if I used I(C1).

The reason for this is I rotated C2 180 degrees when I drew the schematic.

If you look at the SPICE netlist you can see this:

Code: [Select]

C1 v_c1 0 1u IC=1
C2 0 v_c2 1u IC=1
R1 v_c1 0 1Meg
R2 v_c2 0 1Meg
.tran 3 uic
* Intial Conditions
.backanno

The IC has a sign, it assumes that the first node is the positive node.

C1 node_1 node_2 1u IC=1

Means node_1 is 1V with respect to node_2

It is the same for currents.

Yes I see that, but I didn't rotate any capacitors according to my netlist (.asc file)

Code: [Select]

C1 v_c1 0 1.2n IC=100
L1 0 N003 1µ
R3 N001 v_c1 14
C2 v_c2 0 1.2n IC=100
L3 0 N002 1µ
R1 N002 v_c2 14
B3 N001 N003 I=-I(C2)*2
.tran 1u
* RLC circuit
* Mirror circuit
.backanno
.end

So could could the difference in dc level have something to do with inductor BEMF?

You'd add the following on the schematic instead:

Code: [Select]

.ic V(v_c1)=1 V(V_c2)=1

Unambiguous and doesn't rely on any particular orientation of the parts (which I think is nasty.)

Great tip, thank you.

[Jay_Diddy_B]

Hi,

You get two different answers if you add 'uic' to the simulation statement.

.tran 1u uic

If you don't  have UIC I(L1) starts at 7.14A which is 100V/14

If you have UIC the inductor current I(L1) starts at 0.


Regards,
Jay_Diddy_B

[Jay_Diddy_B]

Hi,
Consider this model, it is a simpler version of your model:


The capacitor current will flow in the circuit on the left till the capacitor is discharged to zero volts.

In the circuit on the right the current is forced to be twice the circuit on the left so the capacitor on the right is charged to -100V then the current stops.

Jay_Diddy_B

[Gaktyt]

You get two different answers if you add 'uic' to the simulation statement.

Yes you are right because the initial conditions are different, so they yield different results.

Why would you use the .uic directive instead of letting LTspice calculate/resolve the DC operating point?

Consider this model, it is a simpler version of your model:

Yes it's simpler, but it is also a RC circuit, my circuit is a RLC circuit, so I would say they are different - not only simpler.

But it makes me think, how do I put an initial condition on the inductor so that it starts at zero current? (I found out .IC I(L3)=0)

[SiliconWizard]

You get two different answers if you add 'uic' to the simulation statement.

Yes you are right because the initial conditions are different, so they yield different results.

Why would you use the .uic directive instead of letting LTspice calculate/resolve the DC operating point?

As you saw, LTSpice in particular and Spice in general need explicit initial conditions in somes cases. In particular, if you don't do so, initial voltage across capacitors (and current through inductors) is not guaranteed to be zero. And yes, it can be confusing.

[Gaktyt]

As you saw, LTSpice in particular and Spice in general need explicit initial conditions in somes cases. In particular, if you don't do so, initial voltage across capacitors (and current through inductors) is not guaranteed to be zero. And yes, it can be confusing.

Yes I can understand that. But even with .ic I(L3)=0 I(L1)=0 the DC voltage level of the left circuit (with *2 current injected) is still equal to the initial capacitor voltage but with opposite sign, and I still can't understand why/how it is so, and I would very much like to learn which mechanism in the circuit that is responsible. I'm still guessing it has something to do with inductor BEMF though.

[Jay_Diddy_B]

Yes I can understand that. But even with .ic I(L3)=0 I(L1)=0 the DC voltage level of the left circuit (with *2 current injected) is still equal to the initial capacitor voltage but with opposite sign, and I still can't understand why/how it is so, and I would very much like to learn which mechanism in the circuit that is responsible. I'm still guessing it has something to do with inductor BEMF though.

This is not really a SPICE or LTspic, it is an analog circuit design question.

First you have to remember that a current source has infinite impedance. Obviously if the current is zero there is no movement of charge.

Second

CV=It

In the master circuit the capacitor is discharged from 100V to zero.

In the controlled circuit

the current is double

so the change in voltage is double.

200V instead of 100V

since you start at 100V and the current direction is negative you end up at -100V.

Consider this model:



A parameter called multiplier is being stepped through the values 1, 2 and 3


These are the results:



The change in voltage on C1 is equal to the change in voltage on C2 x the multiplier.

Jay_Diddy_B
 with multiplier.asc (1.19 kB - downloaded 64 times.)

[Gaktyt]

This is not really a SPICE or LTspic, it is an analog circuit design question.

Sorry about that, I was not sure what to call it.

First you have to remember that a current source has infinite impedance. Obviously if the current is zero there is no movement of charge.

So a "B" source in LTspice has infinite impedance? Does that infer e.g. if I hypothetically made the circuit and injected the current with a BCI probe I would not see the same result as in the simulation? 

The change in voltage on C1 is equal to the change in voltage on C2 x the multiplier.

Check, got it, thank you very much for clearing that up for me.

since you start at 100V and the current direction is negative you end up at -100V.

I'm sorry, I don't understand that part of negative current, I mean it do make sense to me, but it's negative in relation to what?  I only put a (-) minus in front because otherwise the current wave form of the controlled circuit would be inverse, so my confusion is that in both circuits the current wave form is the same (except for amplitude obviously) but you talk about negative current? Could you please elaborate on that?

[Jay_Diddy_B]

Hi,

In SPICE a BI is a Behavioral current source. The current is described by an expression.

It is not that it is behavioral or in SPICE, but any true current source has an infinite output impedance.

Similarly any voltage source has zero impedance.

Consider this:



If you look at the current in R3 or L3 it is always equal to 1A. The current source I1 is forcing the current to be 1A

The voltage across the current source is equal in value and opposite in sign to all the other voltage is in the loop. This is Kirchhoff's voltage law.

Current flow has direction. Take a rechargeable battery, during discharge you can say you have positive current, current is flowing out of the battery. During charging you have current flowing into the battery you can call this negative current.
You have positive and negative currents, just like you have positive and negative voltages.

Regards,
Jay_Diddy_B

[SiliconWizard]

A related note regarding current sources in Spice.

By default, they are ideal current sources. So the simulation will "force" the set current through the circuit, even if that would be physically impossible (in other words, it has no notion of voltage compliance). That can lead to very weird results in some cases.

LTSpice has an interesting option for current sources: you can set them as "active loads". They will then act more or less as you would expect a current source in a real physical circuit.

[SilverSolder]

A related note regarding current sources in Spice.

By default, they are ideal current sources. So the simulation will "force" the set current through the circuit, even if that would be physically impossible (in other words, it has no notion of voltage compliance). That can lead to very weird results in some cases.

LTSpice has an interesting option for current sources: you can set them as "active loads". They will then act more or less as you would expect a current source in a real physical circuit.

Interesting, how do you do that?   I don't see "Active Load" in Help

[Jay_Diddy_B]

Hi,
You check this box:



Regards,
Jay_Diddy_B

[Jay_Diddy_B]

Hi,

This is how it behaves:






It is useful in modelling power supplies, because it doesn't pull the output negative.

Regards,
Jay_Diddy_B

[Gaktyt]

If you look at the current in R3 or L3 it is always equal to 1A. The current source I1 is forcing the current to be 1A

You say "forcing", could the current source be placed differently so that it "adds" current instead of "forcing"?

The voltage across the current source is equal in value and opposite in sign to all the other voltage is in the loop. This is Kirchhoff's voltage law.

Check, and thank you for making that clear to me, I appreciate it.

I'm still not completely sure that I understand the voltage in the circuit because; after the current is zero the voltage remains -100V (current*2) forever, so I'm in doubt if -100V is the new 0V? And if it is the new 0V, then what is the initial capacitor voltage? or when in time does -100V become the new 0V? Or maybe I should make a new post for this question?

[Gaktyt]

LTSpice has an interesting option for current sources: you can set them as "active loads". They will then act more or less as you would expect a current source in a real physical circuit.

The Behavioral Current Source doesn't seem to have this option, or maybe it is set somewhere else?

[SiliconWizard]

LTSpice has an interesting option for current sources: you can set them as "active loads". They will then act more or less as you would expect a current source in a real physical circuit.

The Behavioral Current Source doesn't seem to have this option, or maybe it is set somewhere else?

Yes, it doesn't. It directly maps to a Spice 'B' source, whereas I suspect that the more basic current source is an improved model in LTSpice.

So if you're using that, I guess the only way you can add that feature is to include it in the formula expressing the current. Read LTSpice's help on "Arbitrary Behavioral Voltage or Current Sources". You'll find out there's quite a lot you can use for expressing the current.