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| LTspice current injection |
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| Gaktyt:
Hi, I made the following simulation in LTspice in an attempt to simulate current injection. I do not understand why the voltage DC level of the left circuit (with *2 current injected) is equal to the initial capacitor voltage but with opposite sign? Any thoughts on that would be appreciated. |
| SiliconWizard:
I've used '.ic' spice directives on LTSpice schematics, but never the individual "IC" parameter for a given component that you seem to be using. I haven't even seen how to set them in LTSpice. What version are you using? Also, why is B3 dependent on I(C2)? |
| Jay_Diddy_B:
Hi, Please add your .asc file to your post. When I run this model I get a similar result to what you are reporting. The reason for this is I rotated C2 180 degrees when I drew the schematic. If you look at the SPICE netlist you can see this: --- Code: ---C1 v_c1 0 1u IC=1 C2 0 v_c2 1u IC=1 R1 v_c1 0 1Meg R2 v_c2 0 1Meg .tran 3 uic * Intial Conditions .backanno --- End code --- The IC has a sign, it assumes that the first node is the positive node. C1 node_1 node_2 1u IC=1 Means node_1 is 1V with respect to node_2 It is the same for currents. Regards, Jay_Diddy_B |
| SiliconWizard:
--- Quote from: Jay_Diddy_B on May 29, 2020, 05:01:57 pm ---Hi, Please add your .asc file to your post. (Attachment Link) When I run this model I get a similar result to what you are reporting. (Attachment Link) The reason for this is I rotated C2 180 degrees when I drew the schematic. If you look at the SPICE netlist you can see this: --- Code: ---C1 v_c1 0 1u IC=1 C2 0 v_c2 1u IC=1 R1 v_c1 0 1Meg R2 v_c2 0 1Meg .tran 3 uic * Intial Conditions .backanno --- End code --- The IC has a sign, it assumes that the first node is the positive node. C1 node_1 node_2 1u IC=1 Means node_1 is 1V with respect to node_2 It is the same for currents. Regards, Jay_Diddy_B --- End quote --- I didn't know about this IC parameter and never used it. But given what it does, I think that's one more reason to stick to .ic directives. You'd add the following on the schematic instead: --- Code: ---.ic V(v_c1)=1 V(V_c2)=1 --- End code --- Unambiguous and doesn't rely on any particular orientation of the parts (which I think is nasty.) |
| engrguy42:
Yeah, if you CTRL-RT CLICK on a capacitor, for example, you can set initial conditions by doing a "IC=0" on the SpiceLine. But it sucks that you have to do that. Who the hell thought that one up? They should all default to zero. Geesh. That messed me up just the other day doing a time controlled switch closing into a capacitor. |
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