Good enough explanation, ya.
If you really want to get dirty, it'll require thinking about the vias as sections of single wire transmission line, bridging between parallel planes (also transmission lines, of various dimensions, impedances and resonant modes).
The general effect is to reduce the impedance between points. A secondary effect is the trapping of waves (modifying, or creating new resonant modes), which can be undesirable (points between vias acting as resonators, and thus coupling signals into traces). But, this is only applicable to wavelengths on the order of the via separation: thus, if you don't have signals in the GHz, a via separation distance of inches will be more than good enough. The impedance is also quite low in general (the effective waveguide thus formed between top and bottom copper has a high aspect ratio), so signals couple poorly into and out of it (from ~50-100 ohm traces), and the resonators have low Q (the vias aren't terrifically conductive).
The most important for signal integrity is to make sure, anywhere a trace crosses a discontinuity (e.g., a cut in the surrounding or underlying pour), that discontinuity should be bypassed across. For cuts in ground plane (e.g., due to traces crossing at right angles on a two layer board), those can be stitched. If the construction has ground on one side and VCC on the other (for example), discontinuities in a given layer can be shorted across with jumpers (or vias and traces), but obviously, can't be stitched top to bottom (they're different nets). If the construction has one pour ending (e.g., GND) and another beginning (e.g., VEE as the traces enter an analog section), the boundary between the planes should be stitched with bypass capacitor(s) in exactly the same way as any other example here.
In multilayer construction, the plane-plane impedance is typically so low (< 10% of the trace impedance) that the amount of signal coupled into it is extremely small, even over discontinuities such as these. Or another way to think of it: as long as there is an underlying pour uniting the board (e.g., a 100% coverage GND layer), it matters much less whether you have cuts in other layers (e.g., going from +3.3V to +5V domains, with their respective independent pours on the VCC layer), for when traces cross over those cuts.
Tim