Clock generation with passive crystals

[pyrohaz]

Hi,

I'm wanting to interface a Wolfson sigma delta DAC through I2S. Unfortunately, my STM32F0 board can produce the sufficient I2S signals but it doesn't produce the clock signal permanently which is required for the Wolfson IC. I could use the MCO output etc but for portability, I want to use a seperate dedicated master clock for the DAC. With regards to the DAC, I'm wanting to use the WM8762GED. I'm using a 48kHz sample rate and with an oversampling ratio of 512x, this results in the DAC requiring a 24.576MHz clock. Fortunately, this is a pretty standard crystal which makes things a lot easier! It also means I can use a 96kHz sample rate in the future oversampled to 256x or 32kHz with 768x oversampling. So what I'm here to ask: I know that you can create a clock using a crystal, two capacitors, a series resistor (sometimes required?) and an inverter. I'd like to use a standard HC49 crystal. Whenever I'm doing this with a standard microprocessor, a pair of 18pF/22pF capacitors always ensures that the crystal starts correctly though I don't have the equipment to accurately measure the frequency at which it is oscillating.

With regards to this application however, is the capacitance required dependent on frequency or crystal package? One of the crystals I'm looking at on RS states an 18pF capacitance (http://uk.rs-online.com/web/p/crystal-units/6938838/). With respect to the inverter, I'd rather not use a full 74HC69 package or 4069 so I'm looking at the fairchild range of single package logic gates - notably the MC74VHC1G04. What I'm wanting to know however is whether this inverter will be fast enough to drive the crystal and produce the required clock frequency? A propagation delay of 7.1ns into a 15pF load at 3.3v is stated though under my conditions, the capacitance would be higher so I'd expect to take longer. Regardless, surely that propagation delay should allow for >100MHz operation? What are the main parameters to look for with respect to using inverters to drive crystals and produce oscillations? The inverter also states an input capacitance of maximum 10pF but typically 4pF. This coupled with PCB capacitance should surely be considered when choosing the load capacitors for the crystal, right?

Any help is appreciated!

Cheers,
Harris

[pyrohaz]

As a further note, I think I will require two inverters, one to produce the oscillations and the other to buffer the output of the first inverter. Is this a correct assumption?

[bktemp]

If I understand it correctly, you want to use a completely seperate master clock with no correlation to the audio signal. This basically works, but produces unwanted spectral components in the output signal since the codec must duplicated or skip audio samples if one clock is faster or slower than the other one.

[pyrohaz]

Ah, yes that makes sense. Would the audio artifacts be particularly noticeable or would the dramatically impact the audio quality? I think the SPI bit clock output is at a constant frequency (emitting 2 samples at 48KHz, meaning a clock rate of 768kHz. Could I potentially use some form of small PLL to multiply this frequency by 16 or 32 to get to the required master clock?

Harris

[macboy]

Ah, yes that makes sense. Would the audio artifacts be particularly noticeable or would the dramatically impact the audio quality? I think the SPI bit clock output is at a constant frequency (emitting 2 samples at 48KHz, meaning a clock rate of 768kHz. Could I potentially use some form of small PLL to multiply this frequency by 16 or 32 to get to the required master clock?

Harris

at 48 kHz, and 2 channels, you will have at least 16b * 2 * 48 = 1536 Mbps. Usually, 32 bits are sent per sample, even if only 16 are valid. So the data rate (and bit clock) would be 3.072 MHz.

You can use a simple clock multiplier chip to produce a multiple of the bit clock to use as a master clock. I'm familiar with ICS502, 511, 512, etc. but there are many out there from many manufacturers. One 8 pin chip with no additional components will do it.

[bktemp]

It depends on the codec how well masterclock to samplerate differences are handled. I have seen some codecs that even mute the audio for some time whenever there is a too large phase difference.
The WM8762 seems to be one of them:

The WM8762 has a master clock detection circuit that automatically determines the relation
between the master clock frequency and the sampling rate (to within +/- 8 master clocks). If
there is a greater than 8 clocks error, the interface shuts down the DAC and mutes the output.
The master clock should be synchronised with LRCIN, although the WM8762 is tolerant of
phase differences or jitter on this clock.

There are some codecs with integrated plls that generate their master clock from the samplerate. Another possibility: Divide the master clock by 8 to get the bitclock. Most controllers support using an external bitclock.

[David Hess]

With regards to this application however, is the capacitance required dependent on frequency or crystal package? One of the crystals I'm looking at on RS states an 18pF capacitance (http://uk.rs-online.com/web/p/crystal-units/6938838/).

The crystal is cut with a specific load capacitance in mind.  If the load capacitance is changed, then the oscillation frequency will be different but the effect is small.

With respect to the inverter, I'd rather not use a full 74HC69 package or 4069 so I'm looking at the fairchild range of single package logic gates - notably the MC74VHC1G04. What I'm wanting to know however is whether this inverter will be fast enough to drive the crystal and produce the required clock frequency? A propagation delay of 7.1ns into a 15pF load at 3.3v is stated though under my conditions, the capacitance would be higher so I'd expect to take longer. Regardless, surely that propagation delay should allow for >100MHz operation?

When using a logic gate in this way usually it operates in linear mode so digital propagation delay is a poor measurement compared to phase shift at the frequency of interest.

You generally do *not* want a logic gate which is too much faster than necessary because it will encourage parasitic oscillation.  For the same reason, unbuffered logic gates are preferred.

What are the main parameters to look for with respect to using inverters to drive crystals and produce oscillations? The inverter also states an input capacitance of maximum 10pF but typically 4pF. This coupled with PCB capacitance should surely be considered when choosing the load capacitors for the crystal, right?

Parasitic and device capacitance count toward the load capacitance on the crystal.

Linear Technology application note 12 is worth reading on this subject:

http://www.linear.com/docs/4108

[pyrohaz]

Ah, yes that makes sense. Would the audio artifacts be particularly noticeable or would the dramatically impact the audio quality? I think the SPI bit clock output is at a constant frequency (emitting 2 samples at 48KHz, meaning a clock rate of 768kHz. Could I potentially use some form of small PLL to multiply this frequency by 16 or 32 to get to the required master clock?

Harris

at 48 kHz, and 2 channels, you will have at least 16b * 2 * 48 = 1536 Mbps. Usually, 32 bits are sent per sample, even if only 16 are valid. So the data rate (and bit clock) would be 3.072 MHz.

You can use a simple clock multiplier chip to produce a multiple of the bit clock to use as a master clock. I'm familiar with ICS502, 511, 512, etc. but there are many out there from many manufacturers. One 8 pin chip with no additional components will do it.

Woah! There is a dedicated chip that does all I want in a nice simple package, really appreciate this find, thanks!

With regards to this application however, is the capacitance required dependent on frequency or crystal package? One of the crystals I'm looking at on RS states an 18pF capacitance (http://uk.rs-online.com/web/p/crystal-units/6938838/).

The crystal is cut with a specific load capacitance in mind.  If the load capacitance is changed, then the oscillation frequency will be different but the effect is small.

With respect to the inverter, I'd rather not use a full 74HC69 package or 4069 so I'm looking at the fairchild range of single package logic gates - notably the MC74VHC1G04. What I'm wanting to know however is whether this inverter will be fast enough to drive the crystal and produce the required clock frequency? A propagation delay of 7.1ns into a 15pF load at 3.3v is stated though under my conditions, the capacitance would be higher so I'd expect to take longer. Regardless, surely that propagation delay should allow for >100MHz operation?

When using a logic gate in this way usually it operates in linear mode so digital propagation delay is a poor measurement compared to phase shift at the frequency of interest.

You generally do *not* want a logic gate which is too much faster than necessary because it will encourage parasitic oscillation.  For the same reason, unbuffered logic gates are preferred.

What are the main parameters to look for with respect to using inverters to drive crystals and produce oscillations? The inverter also states an input capacitance of maximum 10pF but typically 4pF. This coupled with PCB capacitance should surely be considered when choosing the load capacitors for the crystal, right?

Parasitic and device capacitance count toward the load capacitance on the crystal.

Linear Technology application note 12 is worth reading on this subject:

http://www.linear.com/docs/4108

Ah! I see now, I found some unbuffered single gate ICs which stated that they were suitable for clock generation circuits so I'll definitely be keeping this in mind in the future. Also, thanks for the link, its an interesting read! I don't actually have much knowledge of TTL logic (a retro 74xx noob I'm afraid!) so its nice to learn about it in a practical application.

It depends on the codec how well masterclock to samplerate differences are handled. I have seen some codecs that even mute the audio for some time whenever there is a too large phase difference.
The WM8762 seems to be one of them:

The WM8762 has a master clock detection circuit that automatically determines the relation
between the master clock frequency and the sampling rate (to within +/- 8 master clocks). If
there is a greater than 8 clocks error, the interface shuts down the DAC and mutes the output.
The master clock should be synchronised with LRCIN, although the WM8762 is tolerant of
phase differences or jitter on this clock.

There are some codecs with integrated plls that generate their master clock from the samplerate. Another possibility: Divide the master clock by 8 to get the bitclock. Most controllers support using an external bitclock.

Oh! Thats annoying. It seems that finding a PLL which can happily multiply by 512 is somewhat harder than I thought, unless I'm just looking in the wrong places? I didn't read that in the data sheet so thats annoying! Thank you for point it out to me however.

[tszaboo]

You can run your signals through an Asynchronous Sample Rate Converter like SRC4190 and use your chosen reference clock.

[David Hess]

Ah! I see now, I found some unbuffered single gate ICs which stated that they were suitable for clock generation circuits so I'll definitely be keeping this in mind in the future. Also, thanks for the link, its an interesting read! I don't actually have much knowledge of TTL logic (a retro 74xx noob I'm afraid!) so its nice to learn about it in a practical application.

I have had good results with HC logic even when unbuffered gates were not used (HCU) but I never thoroughly tested for operating margin.

Most of the actual TTL gate oscillators I have seen used low power TTL and I am not sure why.  My guess is that was to limit the gain-bandwidth product in linear mode to prevent spurious oscillations.

Transistor based crystal oscillators are generally more reliable and have higher performance.