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M-bus master, subtracting quiescent current from data signaling.
HSPalm:
Hi,
I'm looking into designing an M-bus master implementation. There are many details to comprehend and implement in the end, but the basics of the signaling between master and slave goes like this (my understanding):
- Bus voltage is nominal 36 Volts
- Master transmits signals by shifting bus voltage levels between 36 Volts and 24 Volts (36 Volts=mark=1 and 24 Volts=space=0).
- Slave transmits by switching in a constant current driver of 11-20mA (quiescent current=mark=1 and quiescent+11-20mA=space=0)
One slave has a quiescent current of N*unit load where Nmax I believe is 4 and a unit load is 1.5mA max. So one slave can have a quiescent current of up to 6mA. If I have 2 of these slaves the bus is already pulling over 12mA, which makes me implement a way of sensing quiescent current on the bus so I know what is signaling from slave or not.
This is a quote from a pdf I found that sums it up:
--- Quote ---The
repeater must adjust itself to the quiescent current level (Mark), and interpret an increase of
the bus current of 11-20 mA as representing a space. This can be realized with acceptable
complexity only when the mark state is defined as 36 V. This means that at any instant,
transmission is possible in only one direction - either from master to slave, or slave to master
(Half Duplex).
As a result of transmission in the master-slave direction with a voltage change of 12 V, and in
the answering direction with at least 11 mA, besides remote powering of slaves a high degree
of insensitivity to external interference has been achieved.
--- End quote ---
My question is if anyone will help me identify an okay implementation, and if maybe a circuit like this has a name already? The available chipsets are for slaves only, and the circuits examples I've seen for masters can only accommodate a fixed amount of slaves within a small range.
The document I quoted is MBDOC48.PDF from the top of this page: http://www.m-bus.com/files/
W4A21021.PDF is the most comprehensive in terms of detailed specifications, but it's listed as "Proposal for new M-Bus Standard"
coppice:
As far as I know there is no integrated M-Bus master chip. The production volume of masters is so much smaller than the slaves, nobody seems to have invested in a custom part. Even for the slave chips there is little competition - basically its just TI and On.
One of the M-Bus documents contains a reference design for a discrete M-Bus master, which many people use as a starting point for their own designs. I had a quick scan through the documents at www.m-bus.com, and I can't spot where it is, but its definitely out there somewhere. You might find something by hunting through the TI web site.
coppice:
I just remembered that there is a schematic for a very simplistic M-Bus master at http://www.m-bus.com/files/minimaster.tif, which is only suitable from talking to a couple of meters on the bus. That is not what I was referring to in my previous message. There is a schematic for a serious design in one of the M-Bus documents, capable of talking with a large number of meters on the bus.
HSPalm:
--- Quote from: coppice on March 20, 2017, 12:07:35 pm ---I just remembered that there is a schematic for a very simplistic M-Bus master at http://www.m-bus.com/files/minimaster.tif, which is only suitable from talking to a couple of meters on the bus. That is not what I was referring to in my previous message. There is a schematic for a serious design in one of the M-Bus documents, capable of talking with a large number of meters on the bus.
--- End quote ---
Okay, I've not seen anything more extensive than the one you linked. Thanks for helping out!
I've started on a receiver-circuit that uses a comparator and a sense resistor. The idea is that the same signal is fed into both comparator inputs, only slewed by a low pass filter on the negative input so it will remember the input voltage while the capacitor discharges. Any fast changes in current consumption will show in the direct input, but not in the LPF input, and \so the output only swings with the sudden changes in current.
- R1 is the sense resistor, 0.25 watt, which in worst case must pass 0.5 A.
- R3 and R4 is the voltage divider to bring input signal at least 1.5 V below comparator supply pin.
- R6 is offset adjusting the inputs to make sure the input signal swings past the reference pin.
- R2 and C1 is LPF.
To me this looks like a good design so far, but I want your input... I want it to function at quiescent bus currents from 1 to 64 unit loads, which means detecting 11-20 mA currents on top of 1.5 mA to 96mA of quiescent current. I'm not quite sure how long a data packet can last in number of bytes, but I want it to receive at least 1 second at a time at 300 baud (sounds sufficient?). Higher baudrates is easier.
I understand that this circuit will not be able to detect bus collisions. Which I must find out if I really need or want.
HSPalm:
I finished the design and it works for all three baud rates (300, 2400 and 9600). Does anyone have anything to say about the design before I order a PCB for it? If anything is unclear, please ask. I tried to make the schematic as tidy as possible and using net names for the important signals. In the picture I'm simulating quiescent current of 200mA at 300 baud..
The transmit part is simply switching slave ground connection though a 12V zener to subract 12V from the overall bus voltage.
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