Ah, that's more normal.
So, gate impedance, as in impedance to the gate -- anywhere in the S-G loop would do but simply a series resistor at the gate is most likely. For a beefy transistor like that, just a few ohms should do. It can be a few kohms and it doesn't matter, everything's quite slow here.
Note that the input side has no discharge when it's switched off, so the only path for the gate capacitor to discharge is through the transistor itself, and load. And it'll turn off once it's down to a few volts, and discharge will level off to around Vgs(th).
A smaller capacitor can be used, and larger resistor; doesn't really matter. Gate leakage is quite low, that's all you need to overcome.
To get faster discharge, a S-G resistor can be used; just in parallel with the zener. This increases the minimum turn-on voltage, since it makes a voltage divider at low voltages (before the zener is conducting). I'm guessing input is always in the vicinity of 48V so that's not a problem. (Indeed you can dispense with the zener if the input really is consistent, but the zener is a good precaution to protect the gate in case anything weird happens.)
Note that, for fast charge rates, the energy stored in C2 must also be dissipated in M1. Which is 5.5J, so good luck getting that into any single-die transistor for short periods of time (10-100us?) -- even the largest transistors hardly do 1J (often shown in the avalanche rating, which is also a short duration, high dissipation test).
For longer startup times, the energy rating goes up -- basically, more of the die, lead frame, component body, etc. is able to heat up -- but so too your load dissipation. For short risetimes (much less than C2*R3), you can essentially say it's charging a capacitor and that's it; but for longer time scales, the load current will have a significant impact on transistor dissipation.
The limiting case being for an extremely slow rise, which will dissipate a maximum continuous 120W in the device (because the load resistor is 480W continuous, maximum power point is at half output voltage or 24V, at which each device (M1, R3) is dissipating 120W for a total of 240). Which clearly isn't going to happen with that part (but a TO-247 on generous heatsink, could).
Somewhere between these extremes, you need a device big enough to provide adequate pulsed-power dissipation. This is shown on the SOA (with a series of curves for different pulse widths) and transient thermal impedance (curves for different duty cycles; this is a single cycle event).
I don't know offhand just how big of a device you'll need for this much capacity, and what risetime will be best suited to it. I have a sneaking suspicion that a TO-247 or D3PAK style device will be needed.
BTW, if you want a smoother voltage slope, consider adding some capacitance from D to G (again, keeping a resistor to the gate pin itself, to stop possible oscillation). This is effectively multiplied by Miller effect, so not much is needed (say 1/100th that of G-S). The reason for the lumpy rise is twofold: one, transconductance increases with Vgs, so it accelerates to begin with (into a fixed load resistance, it's usually about a parabola); two, Cdg internal to the component (Crss on the datasheet) serves the same function but varies wildly with Vds. Which is probably in part why your simulation kind of rounds off at the top corner, but also it's not clear how accurately the SPICE model has captured this characteristic (it's so nonlinear, SPICE has trouble representing it, and often a custom model is needed in addition to the somewhat-more-ideal MOSFET model used internally), so you may find different results in practice.
Tim
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