Make use of an old CGA monitor

[miguelvp]

Well I got to 640x200 but had to bypass the LUT because its causing me some timing issues and it would not display the colors that I wanted.



Even without the LUT the image is not stable if I put a high frequency pattern in just black and white. It doesn't loose lock but I see some noise in the image.
I guess I could reroute signals in the fabric to meet the needed timings.



I'm running the master clock at 24MHz that gives me 25.500MHz instead of the asked 25.125MHz so I guess I should use an external oscillator with better precision if I want to go this high and with a lot of switch on/off.

VSynch fall time is ~6ns, rise time ~30ns
The video going on/off per pixel makes the rgb signal to have a rise and fall time of ~15.5ns

Still I think it can be tweaked to get it more stable, but I think 640 is about the maximum I can get out of this PSoC. I would use the higher frequencies (up to 80MHz) but the PLL only operates with an input between 1MHz to 48MHz. When selecting 48MHz with the built in oscillator I get 24MHz out, I still can make the monitor lock and it runs without so much noise but I still have to bypass the LUT.


Well I did increase the PLL output to ask for 50.350 MHz and using the internal IMO at 48MHz it's giving me 51.000MHz so I can half that and get 25.5MHz. Running the IMO at 24MHz and asking for 50.350 it gives me 50.400 MHz so I'll end upt with 25.200 which is pretty close. The maximum output of the PLL is 80MHz, maybe I can ask for triple (75.525) but oh well, I think there are still ways to get the 640x200 stable.

Or use a D-FlipFlop to half the frequency, or use one of the many modules they have, so I haven't given up but this might require more work, but if 640x200 with two colors is not that important it can do the rest with no problems.

[ranch varment]

Thats so cool, I didnt know monitors had an extension on their input to communicate with pixel blocks?

[miguelvp]

Thats so cool, I didnt know monitors had an extension on their input to communicate with pixel blocks?

Not quite but close enough, it's just a serialization of data controlled by horizontal and vertical syncs. But the "communication" is unidirectional, as in output from the video controller to the display.

The monitor uses the horizontal sync to determine the raster speed from left to right, on old analog CRTs that will directly drive the horizontal deflector to sweep the electron beam left to right.

The vertical sync does the same but for the Vertical deflection coil that determines the y deflection over time. Also when on a retrace the electron gun is off during the sync pulse. The intensity of the beam is controlled by the analog voltage per color component (between 0-0.7V, with a 75 Ohm termination).

Even modern HDMI uses the same raster serialization but it's control via the data channels so It's a bit more complicated with modern monitors but in essence it's still the same.

[miguelvp]

Got the timings figured out and added the CGA 2K sprites:

I'm skipping every other line so it's not too busy, also I added a space in between characters for the same reason.

The image is very stable but I want to up the MASTER_CLOCK to 75MHz, right now I'm dividing it to get the needed 25MHz but I could use a frequency divider on the hardware digital blocks and still keep the 75MHz for the BUS_CLK (CPU)

Next step is to put everything together with all the modes, palettes, etc and last but not least the communication protocol over the USB device, maybe I just leave it as RS232 since I could use a USBUART module within the chip.

Also a friend of mine might have a CGA so I can try to make it work on CGA instead of VGA. Or just support both

[miguelvp]

Still no CGA monitor, but got some progress done last night on colors and text, 16 colors 80x25 characters, with the full CGA 8x8 character font loaded on the PSoCs 2KB EEPROM





No flickering at all and very stable. Pixel resolution is 640x200 for the actual pixel frame buffer.
I'm copying from the EEPROM to the frame buffer based on a 80x25 text buffer, and using another smaller buffer to store the colors per character cell.

[miguelvp]

Now with background colors as well, not blink bit implemented yet.


My color pixel clock is one pixel too early, I'll have to figure out how to delay the color by a pixel clock.

My friend at work is going to lend me his monitor so I can check if my CGA timings work over the weekend.

[miguelvp]

So I guess last night I was playing with the colors on my VGA monitor set at 640x400 but displaying really 640x200. Not sure what I was doing but I found this screenshot of altering the 2nd scanline to do something else than the main scanline, since I have really two lines per line.

Well I want this effect for other purposes so the old 15KHz games look like they would on an LCD.

Granted that whatever I was doing made the black on black characters appear grey on the alternate lines, but I think this would be a cool effect so retro games could look like they did.

It's a good thing I have perforce installed and I've been using it, so I can look at what I did. That is if I ever checked it in. but knowing it's possible to get this look on an LCD is good to know.

[P K]

Excellent progress!  Looking awesome!

Those PSoC parts are interesting - I've got a bunch of the v4 PSoC dev boards, the $4 ones with the USB built onto the PCB.  I've been playing with CPLD graphics lately, but it looks like you can do a lot of the logic directly on the PSoC - will have to break one out next and play with it.

[miguelvp]

I would have gone for the PSoC 4 ones but they don't have DMA support on the specific chip they used for that board, I think they did introduce one chip (no devboard) that has at least one DMA channel but not sure.

There might be ways to still transfer the data fast enough for lower resolutions.

Edit:
Link to the $4 PSoC 42xx prototyping chip (CY8C4245AXI-483) datasheet:
http://www.cypress.com/?mpn=CY8C4245AXI-483

It has enough PWMs to drive the HSync and VSync but not much more, no DMA, no EEPROM, not enough SRAM (4KB) and just 32KB of flash.

Link to the $10 main PSoC 5LP prototyping chip (CY8C5888LTI-LP097) datasheet:
http://www.cypress.com/?mpn=CY8C5888LTI-LP097

It also has a 2nd 5LP (the programmer) with 11 GPIOs wired that could be used to drive the display. But then you can't program the other one, so you'll have to preserve the bootloader and bootloadable and I'm not sure if it can be programmed with the miniprog 3, but I guess if you have several 5LP prototype boards you could preserve a couple of the kitprog parts to restore the rest. Seems the SWDCLK and SWDIO are connected to the USB D- and D+ pins and XRES is available so you might be able to repurpose the kitprog part if you have many of them.

Link to the 2nd PSoC 5LP (CY8C5868LTI-LP039) used to program the main one:
http://www.cypress.com/?mpn=CY8C5868LTI-LP039

Only difference is that the programming one can only reach 67MHz while the main one can do 80MHz.

[miguelvp]

Got more progress but in the meantime here is the 2K bitmap font as a 2048x8 pixel png 2 bit black and white.
I had to convert it to.ras format so I could get the raw hex values, then I used a hex editor to convert the hex dump to text and then changed it to the .csv file needed to import the rom.

My first attempt had some of the sprites offset, the original image I used showed several rows so I had to paste them to concatenate them. I guess I could have typed every hex number but that would have taken forever, and I couldn't find the actual rom or hexdump anywhere.

So I'm also including the comma separated values file I used (just remove the .txt that I needed to add so I could attach it).

[miguelvp]

So my friend lent me his Sony Trinitron 13 inch monitor (KV-1311CR) that has RGBI input and actually will work in CGA mode.

I derived the timings from the CGA manual I linked on page 2 or was it 3, the values there are in hex and character based so they have to be converted to decimal and multiplied by 8 and came out with this (for 640x200 @ 63.5Hz):

Code: [Select]

----------------------------------------------
Screen refresh rate  63.5Hz
Vertical refresh     15748 kHz
Pixel freq.   14.236192 MHz

Horizontal timing (line)
 
Polarity of horizontal sync pulse is negative.
Scanline part  Pixels  Time [µs]
Visible area    640    44.955842
Front porch      80     5.619480
Sync pulse       80     5.619480
Back porch      104     7.305324
Whole line      904    63.500127

Vertical timing (frame)

Polarity of vertical sync pulse is negative.
Frame part     Lines   Time [ms]
Visible area    200    12.700025
Front porch      18     1.143002
Sync pulse        6     0.381001
Back porch       24     1.524003
Whole frame     248    15.748031
----------------------------------------------

I did enabled the CGA component on the schematic and wired it on a breadboard.
The pins right to left are: Red, Green, Blue, Intensity, HSync, VSync, Ground. All of them are TTL level (0V-5V).
Edit: USB is just for power but that connector can be used to communicate with the PSoC 5LP as well, UART, SPI, I2C, HID and even MIDI .


The VSync took a while to lock and I had to keep trying to adjust it, maybe the pulse is too big or not big enough, It doesn't help that the monitor takes about 2 minutes to even come on, so maybe it's because it has seen better days, but I'll keep on playing to see if I can make the VSync lock easier. At the moment if I move the VHold just a bit it starts rolling. Also the HSync front porch might need to be smaller because the image is too much to the right and using the "H Cent" on the monitor I couldn't getting totally centered.



I'll have to play with the timings a bit, also I got the pixel clock to 14.222 MHz that's all the PLL would give me. which is close enough to the desired 14.236192 MHz I was aiming for.
Then again maybe my timings are way off because that puts the display at 63.5Hz frame rate. But based on all the docs I could find it seems that should be the case.

[miguelvp]

One more with the lights off and closer:


And a closeup:


Edit: compare to the LCD one that doesn't translate pixel value 6 to brown and it shows as dark yellow on the LCD one. CGA did have a special value for color index 6 and this Trinitron seems to do the translation as well.
Look for the number "1" second row, second column on the image below. 7th column 2nd row above.


The banding (some lines look darker in the image) is interference from the 63.5 Hz and the camera, with my naked eyes there is no banding at all.

Edit: while running it's in between 110 and 120 mW power consumption.

[miguelvp]

So I had to use my scope to adjust the front/back porches for both the horizontal and vertical. Since after fixing why it was hard to get the vertical hold working (I had to keep on sending HSyncs during a VSync and I wasn't). Well it was locking just fine but my screen ended up pushed to the lower right corner of the display.

Meaning that my Front Porch was 0 both on the horizontal and vertical.

First I adjusted the HSync pulse so it would reflect the CGA values I posted earlier. Chan 1 (yellow) is the red color and Chan 2 (blue) is the HSynch signal:



Then took care of the VSync so the pulse will start where is supposed to start. You can see some noise on both HSync (blue) and VSync (yellow) that is caused when there is video output I guess I'm getting a bit of a crosstalk but that's fine because it helps me identify the front and back porch for the VSync pulse:



Edit, the PSoC clock gen lies, it's telling me my pixel clock is 14.222333 MHz but the scope shows me that it's really 14.206061 MHz. All the annotations are done with the 14.222333 one that Creator was telling me what it was.

Edit: (Ideal values are still the ones posted in post #60 at the top of this page, the ones shown here is the closest the PSoC 5LP let me get to).

Result, a happy CGA signal that is dead center in the monitor.



Another closeup, I still have to fix why my color is one pixel too early or better, why are the characters one pixel late.

[zero_budget_tech]

Nothing much to add, but I enjoyed reading this.

Will probably go for a vector display myself, if I ever build the machine I have been thinking about. (8 bit, through hole, front panel input, probably z80)

[miguelvp]

Over the weekend I want to merge this project:
http://www.element14.com/community/thread/24287/l/psoc-4-pioneer-kit-community-project17--2-channel-oscope-with-graphicslcd

To the CGA display making it a cheap 80KHz 2 channel scope. Might be able to push it to 160KHz but it's not going to be earth-shattering by any means

I'm planning to use the BNC adapter I have for my Diligent Analog Discovery to be able to hook the probes.
http://www.digilentinc.com/Products/Detail.cfm?Prod=DISCOVERY-BNC

I'll use the Diligent Analog Discovery as a function generator to find out where the -3dB falls into, so it might take me more than just the weekend

Edit: It would be easier if I could rotate the yoke of the monitor or if I displayed the waves from up to down as the scanline draws the screen for a faster display update rate. But I guess I could use a comparator to know where to draw the current signal bypassing the frame buffer and leaving the signal display all handled by hardware as well, overlayed into the frame buffer.