CPLD Teaching board oscillator

[CM800]

Hi all,

I'm currently working on a MAX V based CPLD teaching board for the college I am attending.
The main advantages of this one is that it is very compact and fits easily into standard prototyping board (2.54mm pitch between ever connector)

Also, any input on the design? I've kept it two-layer, I think if I want all the SMD components on the same layer, I will have to go for 4-Layers, its at the point where it is very crammed there.

I need some advice, what sort of oscillator should I put on the corner?



I'd imagine a 32MHz, 50MHz, 64MHz Crystal, but I'm unsure of the best schematic...

[hlavac]

I'd put a socket for the standard DIL 4-pin oscillator cans, let everyone use what they need, provide one default maybe with the board.
No PLL means you probably want the highest possible frequency oscillator, it can be divided for lower ones.
With the internal oscillator of the Max V you will only need external one for high precision timing, i.e. VGA signal generation etc, so maybe yo ucould get away without one.
Or provide a programmable clock generator chip maybe? Just not the jittery drifting piece of crap Digilent put onto the Basys 2 boards please

[CM800]

I'd put a socket for the standard DIL 4-pin oscillator cans, let everyone use what they need, provide one default maybe with the board.
No PLL means you probably want the highest possible frequency oscillator, it can be divided for lower ones.
With the internal oscillator of the Max V you will only need external one for high precision timing, i.e. VGA signal generation etc, so maybe yo ucould get away without one.
Or provide a programmable clock generator chip maybe? Just not the jittery drifting piece of crap Digilent put onto the Basys 2 boards please

You have a good point, I think I will do that idea with the DIL 4-pin, any other ideas?

What price tag would people be interested in buying these?

[bktemp]

I see one big problem with this board: There are almost no GND pins!
For highspeed digital signals you should have at least 1 GND per 8 digital signal lines.
You have 3.3V/GND on a seperate pin header, but you could easily add 2 GND pins next to pins 28/29 and 30/33 without making the board larger.

[Buriedcode]

Whilst its best to keep things simple, why not a low frequency oscillator?  Perhaps just a single schmitt tigger osc, or a 555 timer with a trimmer.  That way you have a very slow clock to show sequential logic in action rather than have to use some CPLD resources to divide down the crystal osc. 

[CM800]

I see one big problem with this board: There are almost no GND pins!
For highspeed digital signals you should have at least 1 GND per 8 digital signal lines.
You have 3.3V/GND on a seperate pin header, but you could easily add 2 GND pins next to pins 28/29 and 30/33 without making the board larger.

This is planned as a lower frequency board, something for college education primarily, I'm planning to do a fancier one with an ARM processor on it and probibly 4 layer, something to spice things up. I would love to have someone else to work with me on this project if they are interested? Especially if they have VHDL knowledge.

[tggzzz]

Insufficient ground pins.

If transmitting medium speed digital signals over a ribbon cable, it is standard practice to have 1:1 interleaved signal:ground, to minimise all the standard signal integrity problems (crosstalk, impedance, ground bounce etc).

If you aren't transmitting signals over ribbon cables, then twisted pairs are mandatory, and those also need 1:1 interleaved pinouts.

Ignore signal integrity and you will get intermittent operation and/or input/output characteristics that degrade over time.

Medium-speed means edge rates 1ns-5ns, and the period is irrelevant. Virtually all modern logic is in those ranges, and many are <1ns (e.g. 74LVC1G14 is ~600ps).

Also I don't see the decoupling capacitors and ground plane; you must follow the manufacturer's recommendations.

[CM800]

Insufficient ground pins.

If transmitting medium speed digital signals over a ribbon cable, it is standard practice to have 1:1 interleaved signal:ground, to minimise all the standard signal integrity problems (crosstalk, impedance, ground bounce etc).

If you aren't transmitting signals over ribbon cables, then twisted pairs are mandatory, and those also need 1:1 interleaved pinouts.

Ignore signal integrity and you will get intermittent operation and/or input/output characteristics that degrade over time.

Medium-speed means edge rates 1ns-5ns, and the period is irrelevant. Virtually all modern logic is in those ranges, and many are <1ns (e.g. 74LVC1G14 is ~600ps).

Also I don't see the decoupling capacitors and ground plane; you must follow the manufacturer's recommendations.

For cost related reasons, it had to be a two layer board, the decoupling capacitors can be seen on the bottom side of the board near the pins.
I see your points regarding the edge rates, however as this is going for education, the extra pins required would double the board size.
Do you think it should be fine for this kind of use? Or is it really, no doubt, going to be an issue?

[tggzzz]

Insufficient ground pins.

If transmitting medium speed digital signals over a ribbon cable, it is standard practice to have 1:1 interleaved signal:ground, to minimise all the standard signal integrity problems (crosstalk, impedance, ground bounce etc).

If you aren't transmitting signals over ribbon cables, then twisted pairs are mandatory, and those also need 1:1 interleaved pinouts.

Ignore signal integrity and you will get intermittent operation and/or input/output characteristics that degrade over time.

Medium-speed means edge rates 1ns-5ns, and the period is irrelevant. Virtually all modern logic is in those ranges, and many are <1ns (e.g. 74LVC1G14 is ~600ps).

Also I don't see the decoupling capacitors and ground plane; you must follow the manufacturer's recommendations.

For cost related reasons, it had to be a two layer board, the decoupling capacitors can be seen on the bottom side of the board near the pins.
I see your points regarding the edge rates, however as this is going for education, the extra pins required would double the board size.
Do you think it should be fine for this kind of use? Or is it really, no doubt, going to be an issue?

That will depend on the fine details of the implementation, and so it would be unwise of me to comment either way. I suggest you have a look at similar boards and see how they perform.

As for "education", what are you trying to teach? HLLs? Logic? Digital systems? That details matter?  That ESD precautions are advisable? IMNSHO it is a good idea to instill the concept that, unless you are photon-counting or dealing with femtoamps, there is no such thing as a digital signal - only analogue signals that are interpreted by the receiver as digital.

What are the interconnections going to be - boards, jumper wires (=twisted pairs), ribbon cables? It may be possible to reduce the number of grounds to 1:4 or 1:6 or 1:8.

Which is more important, more i/o lines or better signal integrity?

[radar_macgyver]

If by prototyping board you mean the push-in breadboards, having a double-row header on each side would mean that the pins on each column would be shorted together by the breadboard. You'd either have to go to single-row headers, or program the I/O pins going to one half of the header to be tri-state or input.

One way to solve the oscillator issue, assuming each student has access to a signal source, is to provide an SMA or BNC connector on the board, wired to a clock pin. Hook this up to the signal source and you have a programmable clock. In fact, a couple of I/Os on SMA may not be a bad idea, you can use these with cables for any high-speed inter-board I/O. If space is a concern, consider using u.FL connectors and u.FL to SMA adapters; you can buy them for cheap on ebay.

[CM800]

If by prototyping board you mean the push-in breadboards, having a double-row header on each side would mean that the pins on each column would be shorted together by the breadboard. You'd either have to go to single-row headers, or program the I/O pins going to one half of the header to be tri-state or input.

One way to solve the oscillator issue, assuming each student has access to a signal source, is to provide an SMA or BNC connector on the board, wired to a clock pin. Hook this up to the signal source and you have a programmable clock. In fact, a couple of I/Os on SMA may not be a bad idea, you can use these with cables for any high-speed inter-board I/O. If space is a concern, consider using u.FL connectors and u.FL to SMA adapters; you can buy them for cheap on ebay.

Having just talked to my tutor, he thinks that it would be best to have an on-board oscillator. I think DIL solves it. Possibly an SMA connector for external clock, that could be a nice bonus, though I think it might be nicer to do a second revision.

In regards to headers. I intend to send the pinheaders alongside the board, then they could only use half them if they wish (or put them the other way up to access through wires. It also has the advantage of being able to be used on protoboard.

[daveshah]

A random thought but have you considered something like the MachXO2 series from Lattice, which have an integrated oscillator and PLL? The programming circuit is IIRC as simple as an FT2232H so could also be integrated on the board.

[CM800]

A random thought but have you considered something like the MachXO2 series from Lattice, which have an integrated oscillator and PLL? The programming circuit is IIRC as simple as an FT2232H so could also be integrated on the board.

The idea has merit but the college already uses the Altera series and the software, this would be a dropin replacement. (IT at colleges are a NIGHTMARE)