Making my own multislope ADC

[OverlordCheese]

Before I dive in to explaining it, I want to say that take everything that I say with a bucket of salt. I'm not claiming to be advanced in the so-called "voltnut territory". I am enthusiastic about this topic, but... well yea.
https://github.com/Cheesey125/DIY-Multislope-ADC

This project was inspired by NNNI's project, you can easily find him or his youtube channel by looking him up, he's a great guy!

Using NNNI's simulation for the "free-wheeling" architecture, I thought to myself "Why can't this be implemented with multiple slopes", and by that, I meant the part where it is an automated system, but with no code or software whatsoever (unless you count the random number of 0's and 1's in the sequence generator). In fact, unless I am missing something, this basically eliminates the need for highly-optimized code.
I'm finding this hard to explain, so let me just walk you through it step by step:
1) The runup slope is triggered for a set time
2) The output of the integrator goes through a buffer and proceedingly to a network of opamps.
3) There are two parts to this "opamp network" a) the inverting amplifiers b) the noninverting amplifiers. the inverting amplifiers effectively signal when the net charge in the input of the integrator is positive, and vice versa for the noninverting ones.
4) feeding those opamps through some simple logic gates, and we're done with the part that I found hard to explain.
And just to clear any stupidness that I may have no written well, here's a picture of the simulated waveform and a link to the simulation (Fair warning: the simulation isn't exactly pretty)
https://tinyurl.com/y38vwhdm

Finally, there are two more traditional parts (I know that everyone uses residue ADCs, but im not sure about the other thing)
Obviously, I have a poorly implemented residue adc, because I could not find a single true bipolar input one about 12 bits that wouldn't have costed a pretty penny!
Secondly, instead of relying on the speed and accuracy of the timing in GPIO pins, I resorted to an alternative for counting: Counter ics! Specifically, I found this (relatively) cheap 32 bit SPI counter IC: LS7366R..
That's about it for now, I'd appreciate any and all feedback, as I said, don't think I know what I'm doing! (I like to think that, but... there's probably some sort of Vsauce video on it, but it's like when you don't know what you don't know, but you are aware of the fact that you are unaware of something... you are unaware of)

[Kleinstein]

The simulation part misses a synchronization for the reference switching to the clock. Counting times only makes sense if the references are switched in sync with the clock.

Using analog circuitry to control the reference logic can become complicated and for the very small slope parts also error probe (e.g. depends on the OPs / comparator offsets and speed).
There are different ways to control an MS ADC:
1) dedicated logic ( e.g. TTL ICs, ASCIC)
2) A µC / small computer
3) a FPGA or CPLD
Depending on the knowledge / personal preference the choice can vary. One may also combine µC and logic. The timer hardware inside a µC can do some of the critical tasks and make the software less critical. Programming can still be somewhat tricky, using more advanced HW features.

There is no need to use a residual charge ADC. It is perfectly OK to use just the comparator. Even the reset is kind of optional, but usually somewhat (often some 2.5 times - for the common implementation to include a slope amplifier in the reset loop) lower noise than the comparator.

Using an ADC for the residual charge is kind of easy when a µC is used for the control, as many modern µCs include an ADC that can be used. There is no need to have an ADC with bipolar input range - just add some offset.
A residual charge ADC can have a small advantage when it comes to very low noise levels, but it is not a big difference. The ADC in the 3458 still uses just a comparator for the stop and a reset phase.

For the start and not to high a target, one get away with rather few ( 1 or 2) small slopes. So keep it simple. More slope may give a slight speed up, but more complications and precision parts needed.

There is also no need to have both signs for the small slope(s) - it helps to always come from the same direction, as the reaction speed / delay of comparators can depend on the direction.

[OverlordCheese]

Im just using the residue ADC for my later calculations-- If i can detect a voltage, I can plug it into the equation-- or not? I know you are pretty knowledgeable on this subject (I read NNNI's thread), and in the 3458 (Now, dont get me wrong here, I dont stand by this. an NNNI told me this on discord) said they didn't have the tech availible at the time, but I thought with those new ultra low noise comparators that it wouldn't hav e anegative impact on the precision.

As for the start small, get big, there's a problem with that that I cannot easily solve. You see, I'm a kid, and I'm one year off from being allowed to legally work, so I can't exactly afford prototypes. However, I have simulated and... dreamed about it. as for that last comment about the small slopes (If i am interpurting this right), What if i input a negative voltage? wouldn't its precision level be lesser?

[Kleinstein]

Quite some DMMs get away with only 1 slow slope, e.g. the Keithley 2000 and 2002.  For a simulation it is OK to include more, but the simple picture may make things clearer. The main downside of only 1 slope is a somewhat slower (but still very useful) conversion.

With a multi-slope run-up, the sign of the integrator voltage changes not only with the sign of the input. The early HP3455 ADC used small slopes also with both signs. This is possible but causing more trouble than that it helps. It is much better to add an extra phase at the start of the rundown to make sure to have the same sign from there on. This way both signs can be handled the same way. This step was added in the HP3456. The extra step uses a fixed reference for a fixed minimum time, or a litte longer than needed to get the wanted sign.

 The ADC shown seems to use only a simple run-up, still very much like the dual slope ADC. This is perfectly OK for a first test - I started this way too. Later is really makes sense to also have a multislope run-up. This a much more important improvement than multiple fine slopes. The MS run-up and rundown are kind of naturally used together, as the MS run-up allows to use a small capacitor and this makes the use to different slopes much more feasible.

The usual fast comparators have a limited accuracy, as they can have an offset of several mV. So it would become a bit tricky to build the control based on analog set trigger levels of the comparators. For the smaller slopes the trigger levels would be rather close together. With 1 slow slope a 2nd compartor for the control can still be feasible. With even more small slopes this could become tricky in real life.

[OverlordCheese]

Thanks for your reply. Can you clarify what you mean by phases?

As for the multislope run-up, I guess i have my definitions a bit confused and should do some research.

As for the last section, I completely agree, but still; want to find a way to implement this in one form or another. any tips?

[Kleinstein]

The multislope does the conversion in different steps/phases one after the other. The classical form (e.g. 3458) has:

1) the run-up phase with the input active and feedback switching between positive and negative in some ways. The details here can vary a bit.
   The run-up for the simple dual slope ADC is without feedback from the references.
   Multi-slope run-up has feed-back in some PWM way switching between the pos and neg ref. This may again be divided to time steps. 
2) The rundown phase: the input is diconnected and the references are applied to discharge.
3) a reset phase to discharge the integrator to known / fixed starting point.
The reset phase is in theory optional as after the rundown the integrator is essentially discharged. An explicite reset is usually lower noise and allows to wait for a trigger signal to start the run-up phase without much extra delay.
Older MS ADC often also had some analog auto zero step (can be combined with the reset), but this is no longer really needed.

In addition one needs collection of the result and some outout (display or seriel out).
For the implementation it depends on the knowledge one has. Some are better with logic, other know FPGAs/CPLDs and other prefer a µC. The 2 main options today are a FPGA/CPLD  and a µC. Discrete logic is possible but got out of fashon for more complicated parts and the ouput part can add quite a bit.

There is the option to combine some discrete logic for the really time critical parts (e.g. turn off the reference on the next clock cycle after zero corssing of the comparator) and a µC with than less time critical software for the rest and especiall collecting the result and the output. Depending on the µC used the µC internal periphery may be used for some or even all of the time critical parts too. As an example the multislope run-up can be done using the µc internal PWM hardware.