Author Topic: USB layout in top or middle layer  (Read 536 times)

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Offline tiraxinasTopic starter

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USB layout in top or middle layer
« on: April 28, 2022, 12:25:52 pm »
Hi,

High-speed signals routed in the internal layers with GND planes in the adjacent layers have better signal integrity.
1. The USB signals from the top layer to the internal layer using vias. How can be sure that the vias don't create EMI reflections?
2. When is better to route USB signals in external layers instead of internal layers?

 

Offline T3sl4co1l

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Re: USB layout in top or middle layer
« Reply #1 on: April 28, 2022, 04:57:59 pm »
Which USB version are you targeting?

USB1.0/1.1+ "Full Speed" is basically LVCMOS logic level, signal quality is almost irrelevant.  It's differential mainly for benefit of poor quality cables; note that no USB is fully differential, on account of the start/stop symbols, so these still need to come through with adequate fidelity.

USB 2.0+ "High Speed" is more stringent, but also not terrifically fast (480Mbps) so can tolerate mismatched impedances, stub lengths, etc. up to a modest margin (some cm, say).  Easiest: put the PHY right beside the connector, no problem.  If a longer route is required, then consideration of signal quality is worthwhile: matched length traces, characteristic impedance, minimize sharp corners and vias.

USB 3.2+ "SuperSpeed" (5Gbps or more) requires much more care.  Although, are they also doing convenient line coding tricks to help out with that (line or loss compensation, echo cancellation, etc.)?  I don't know, I haven't been keeping up with it.  This will require matched impedances even for short lengths, keeping stubs to a minimum, etc.

In all cases, I think the stub length of a single via is not enough to cause concern.  Impedance tolerances likely aren't tight enough to require special fab.

But yeh, it's all in the standard, freely available, check it out.  You don't need to take our word for it, get it from the source.

As for the shielding effect of inner routing (stripline), this isn't necessary to meet most commercial EMI requirements.  It may be required for more stringent, medical related?, or say aerospace or MIL standards, or say, the use of a conductive (shielded) enclosure and appropriate grounding measures.

Tim
Seven Transistor Labs, LLC
Electronic design, from concept to prototype.
Bringing a project to life?  Send me a message!
 

Offline tiraxinasTopic starter

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Re: USB layout in top or middle layer
« Reply #2 on: April 29, 2022, 07:30:50 am »
Hi,

Thanks Tim for the answer.

We are using USB 2.0 (high speed).
If I use the top layer to route the USB communication and the adjacent layer is the GND plane most of the energy is between traces and GND and the rest will be around the signal. Then this signal is not shielded so can the radiation from outside disturb the signals?
 

Offline T3sl4co1l

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Re: USB layout in top or middle layer
« Reply #3 on: April 29, 2022, 11:24:12 am »
What level of immunity are you targeting?  I think I would start to be concerned for levels above 10 V/m.

Tim
Seven Transistor Labs, LLC
Electronic design, from concept to prototype.
Bringing a project to life?  Send me a message!
 


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