PCIe gen 3 motherboards are always FR4, so I certainly assume it's manageable. Part of what helps is that the traces tend to be pretty short, so even if you're losing some eye opening because of losses in the board itself, you still have enough to be received correctly.
Impedance controlled is really the more important part, because you need to make sure your manufacturer is using materials consistent enough so that your designs don't perform on some batches and fail on others because the dielectric constant isn't consistent, and you want to be sure that the solder resist isn't going to muck everything up either, which should be part of what's controlled in a controlled-impedance fabrication process.
Don't think glass transition temp is going to matter to you, unless your PCIe lanes are going to be routed under power MOSFETs or something, but it can be important in high temperature environments.
If you have any equipment capable of measuring at this frequency, or if you have access to it, you can always verify your work on a test piece. Make a few stripline and surface microstrip connections on the fabrication process you're considering and determine what the losses/crosstalk really are and if that's controlled enough for your application. If your trace lengths start to get long, or otherwise start getting towards the limit of the PCIe spec, though, then your dielectric losses could become much more of an issue.