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MC34063 with external switching transistor

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shadewind:
Hi!

Looking at the datasheet for the MC43063, I can see that the maximum allowed switch current is 1.5A. According to the formulas in the sheet, if I want 1A output, the peak switch current is going to be 2A which is more than the maximum so apparently I need to use an external switching transistor.

So looking at page 7 of http://www.onsemi.com/pub_link/Collateral/MC34063A-D.PDF, there is an example of this. So a few questions:

* A quick search on Farnell with filtering and ordering by price, I found this transistor: http://www.st.com/stonline/products/literature/ds/11763/2stx1360.pdf
It seems to meet all the specs so it should work, shouldn't it?
* If I'm getting this right, the resistor on pin 2 of the device is simply a pull down resistor? What value should be used for this? Is 10k good?
* There is no base current limiting resistor for the external transistor there. Am I supposed to rely on the current limiting capabilities of the MC34063, that is, set Rsc so that the current is limited to the base? Since this transistor has a max base current of 200 mA and let's say we use half of that for safety, then according to the datasheet formula Rsc should be 0.3 / 0.1A = 3?. So a 3.3 ? resistor should do the job then?
* Looks like some of the formulas need adjustment in this case, don't they? Instead of the Vsat listed in the MC34063 datasheet, I'll need to use the saturation voltage of my external transistor instead since it is what is now causing the voltage drop. And while I use the peak base current for the external transistor to calculate the Rsc value, I should still use the peak switch current (2A in my case) for the calculation of the minimum inductance and filter capacitor, shouldn't I?

tecman:
I think your transistor choice should be reconsidered.  The problem is that the configuration you reference is basically a darlington configuration, so you will never truly be saturated, and the additional drop will likely lead to the thermal destruction of the transistor.  You can be 2 volts Vce when on due to the "triple" darlington scheme.  That can be 3 watts at a 50% duty cycle, or about 300+ deg Tjunction.  I like to use a small P channel MOSFET and use the PNP configuration on the right side of page 7.

Your other questions are moot since as a darlington, there is no need for a base resistor, and the saturation voltage is not a function of the data given in the transistor datasheet.  Just as an example, on the 34063 data, the output saturation voltage of the 34063 internal transistors in the darlington configuration is 1.3 volts.  Add another Vbe from your external transistor and you are at 2 volts in the on state.

I like and often design in 34063a's in products, but the internal transistors have limitations and do not do well at higher currents, due to the configuration.  If you do not like MOSFETS, use an external PNP and you can ensure saturation.  Also do not run the transistor near its published limits.

paul

shadewind:
Is the series gate transistor in the schematic required if a P-channel MOSFET is used? The input impedance of MOSFETs is supposed to be very high so the current flowing there is negligible, isn't it?

Anyway, I'm not sure I understand why a Darlington never gets fully saturated. Why is this? If it's not too much to ask for a simple explanation :)

alm:

--- Quote from: shadewind on February 23, 2011, 04:22:16 pm ---Is the series gate transistor in the schematic required if a P-channel MOSFET is used? The input impedance of MOSFETs is supposed to be very high so the current flowing there is negligible, isn't it?

--- End quote ---
The resistance is very high, but there is also the gate capacitance. This can cause both current surges (a capacitor looks like a short if it's empty, or at high frequencies) and oscillations.


--- Quote from: shadewind on February 23, 2011, 04:22:16 pm ---Anyway, I'm not sure I understand why a Darlington never gets fully saturated. Why is this? If it's not too much to ask for a simple explanation :)

--- End quote ---
You should be able to find this in any decent electronics text, or even Wikipedia. The collector of the transistor inside the MC34063 is connected to the collector of the external transistor, so the emitter of the MC34063 transistor is one VCE (sat) below the collector. This collector is connected to the base of the external transistor. The emitter of the external transistor is one VBE below the base. This means that the minimum VCE of the external transistor is VCE (sat) (of internal transistor) + VBE of the external transistor.

The base voltage needs to be higher than the collector voltage to drive a NPN transistor into saturation (all polarities reversed for PNP), which is impossible for the external transistor in a Darlington configuration.

shadewind:

--- Quote from: alm on February 23, 2011, 04:39:53 pm ---The resistance is very high, but there is also the gate capacitance. This can cause both current surges (a capacitor looks like a short if it's empty, or at high frequencies) and oscillations.

--- End quote ---
Ah, so when the FET is first switched on, the "capacitor" will have no charge and thus will act as a short with increasing resistance until fully charged? And this means, I suppose, that I need a series resistor at the gate to limit this current? Won't that also make the switching slower since the charging is slower?

--- Quote from: alm on February 23, 2011, 04:39:53 pm ---You should be able to find this in any decent electronics text, or even Wikipedia. The collector of the transistor inside the MC34063 is connected to the collector of the external transistor, so the emitter of the MC34063 transistor is one VCE (sat) below the collector. This collector is connected to the base of the external transistor. The emitter of the external transistor is one VBE below the base. This means that the minimum VCE of the external transistor is VCE (sat) (of internal transistor) + VBE of the external transistor.

The base voltage needs to be higher than the collector voltage to drive a NPN transistor into saturation (all polarities reversed for PNP), which is impossible for the external transistor in a Darlington configuration.

--- End quote ---
I see. But this problem won't be present if I use a PNP for the external transistor, will it?

In this case, would the formulas be altered in any way and how? I'm a bit unsure of the Rsc value, for example. And what about Vsat?

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