Thanks. This is an attempt to measure two square waves generated by a Xilinx 7z020 using LVCMOS33 signalling into a PMOD port. I suspect I need to work on proper termination to clean up the signal being measured.
One signal is a noisy fractionally divided signal. This is fed back into a PLL on the FPGA.. The other signal is the output from the PLL. The first has a jitter of at least 1.25ns as it is being generated by an 800Msps SERDES output. The seconds has jitter which I suspect is about 200ps. The signal that has the widest variance is the one with at least 1.25ns jitter. It sometimes shows as low as 250ps, which is clearly not correct when viewing the trace on the scope. This makes me suspect both measurements.