RX Data incorrect on TI CC1101 RF Module

[cheeseburger]

Hello

I use two TI CC1101 RF Modules (Chinese Modules - https://www.aliexpress.com/item/1005003781140201.html). Both modules are connected to a Raspberry Pi 2 SBC via SPI.

One of them is doing TX, the other one is doing RX. The TX one is transmitting 8 Bytes every 500ms.

This seems to kind of work, but just kind of. When checking the receive Buffer, it it reports received data like this. Sometimes a bit better, sometimes a bit worse:

Code: [Select]

Bytes in FIFO: 8 
Looks like we have data.. 
Received data: AA 88 AB 22 33 44 44 55 
Flushing FIFO.. 
Bytes in FIFO: 8 
Looks like we have data.. 
Received data: AA 88 AB 22 33 33 44 55 
Flushing FIFO.. 
Bytes in FIFO: 8 
Looks like we have data.. 
Received data: AA 88 AB 22 33 44 44 55 
Flushing FIFO.. 
Bytes in FIFO: 8 
Looks like we have data.. 
Received data: AA 88 AB 22 33 44 44 55 
Flushing FIFO.. 

The sent Buffer is the following one:

Code: [Select]

uint8_t mydata[8] = {0xAA, 0x88, 0xAB, 0x22, 0x33, 0x44, 0x55, 0x66};

So the received Buffer is kind of correct, but just kind of. It changes from time to time a bit (e.g. the third buffer is different than the other ones above). The length is correct, but some Bytes are duplicated.

Is this "normal" Performance for CC1101? Or am I doing something horribly wrong?

I have attached my Code.

[cheeseburger]

Fixed it, the issue was created by not synchronizing the read function to the end of the packet.
Before reading RXFIFO, it must be assured that the end of the Packet already is reached.
This can be accomplished with GDO Pins. I used this Option:

Code: [Select]

Asserts when sync word has been sent / received, and de-asserts at the end of the packet. In RX, the pin will also de-
6 (0x06)
assert when a packet is discarded due to address or maximum length filtering or when the radio enters
RXFIFO_OVERFLOW state. In TX the pin will de-assert if the TX FIFO underflows.