Electronics > Projects, Designs, and Technical Stuff
Memory - die pictures
Noopy:
Let´s start a new topic for memory die pictures.
At first I wanted to split the topic in RAM and ROM but in my view volatile and non-volatile is more convenient:
https://www.richis-lab.de/RAM.htm
https://www.richis-lab.de/ROM.htm
Today let´s take a look into a FRAM, a Cypress FM24V10 (1MBit).
The die is 3,2 x 2,0mm. There is a huge amount of bondpads. Perhaps you can use the die in a parallel configuration too. :-/O
You can spot the big uniform memory area divided in eight columns. There is probably some control circuit on the right side of the die.
The structures are tiny but you can spot the year 2008.
The memory itself is way too small to do a deep dive.
https://www.richis-lab.de/RAM01.htm
:-/O
RoGeorge:
Thank you, subscribed! :)
Noopy:
HML087, you don´t find very much about this chip. It´s a PROM manufactured by Hughes Electronics and can be found in BMW instrument panels.
The die is 2,9mm x 2,1mm.
HML :)
Oh it seems to be a HML069. You find the HML069 in some old universal programmer manuals. It´s a PROM that has to be programmed with 12,25V.
There is a 8C in the metal layer and above it is something like 4A or 4H, probably 4A.
Unfortunately layer 3B is quite hard to read that makes it difficult to analyse the circuit. :-\
Quite some masks: 1A, 2D, 3B, 4A, 5B, 7B, 8C, 11A, 16D
The different crosses allowed them to check the alignment of the masks.
test structures
A big test structure. That´s probably kind of a ring oscillator. There is even a fuse!
Most of the bondpads have the same protection structure.
The output is easy to spot. There is a big highside and a big lowside transistor around it. From the left there comes a differential control signal.
The right bondpad is the high voltage input you need to program the device. It has a different protection circuit.
On the left side of the die there are seven similar looking blocks that get the chipselect and the clock. Three are connected to the line selection. Four are connected to the column selection. That are probably Flip-Flops counting the clock pulses and switching from one memory cell to the other.
Leftmost there are six similar looking blocks connected to the Flip-Flops, probably some support circuit. :-//
On the right side of the die there are eight similar looking blocks connected to the input bondpad. They are controlled by the circuit in the middle which uses the line selection signals generated on the left side of the die. That is probably the latch for the data input. The output of the latches controls the second part of the line selection circuit.
There is a ninth block locking like the latches. It is not connected to the line selection just to the input signal. There are two lines connected to something on the left side of the die. :-//
That´s a good picture of the actual memory. There are 16x8 memory cells. On the left side is the output circuit (it´s connected to the output bondpad). On the top there is the column selection. On the right side there is the line selection (read/write) and on the bottom there is some biasing and control circuit.
Every eight columns have one column selection block. Each column selection block consists of a lowside area and a highside area (in the middle) giving you a push-pull driver for every column.
The output circuit is hard to read. :-//
The line selection is quite complex. On the left side you see four lines going into the memory area (red/green). Every memory line has one red and one green line.
On the right side there is the write circuit. The latches switch the HV or the GND to the red lines.
The green lines are connected to the red lines with the short dark green lines. The yellow transistors are controlled by the line selection generated on the left side of the die.
An overview...
Here we have the memory. It is built out of 2x2 cells. Each cell consists of a floating gate transistor (FG) connected to the red line and a selection gate transistor (SG) connected to the green line that is connected to the output circuit too. A short red line (the "real" red) connects the FG and the SG.
I assume reading a cell is done like this:
The column selection switches a high on the column we want to see. The others are low.
The outer red lines (formerly marked red) are low.
The inner red lines (formerly marked green) are low too except the one we want to select. This one is floating.
The floating gates normally need a mid range voltage to work probably. I assume the high of the column selection is routed to the floating gates by the uppermost line in the lower area. Perhaps the low in the second line is connected to the floating gate line too to get this mid range potential.
Now the combination FG / SG switches the low of the outer red lines to the inner red lines if the floating gate has been programmed active.
I assume the output circuit contains weak pull-ups that are pulled low by the inactive lines. The active line remains high or is pulled low by the FG/SG depending on the data in the FG.
I´m not perfectly sure about that explanation but it seems reasonable.
If you want to write data you just have to select one column no line because you have already eight bit of data in your latches that control all the lines at once.
On the outer red lines (formerly marked red) there is HV if we want to program the FG and a low if we don´t want to.
In the column we want to write the SG is high and with the help of the circuit at the bottom also the FG is high.
The output circuit probably switches a low on the inner red line (formerly marked green).
In this configuration the drain source voltage of the FG transistor is quite high and there is a mid range gate source voltage. The high voltage generates charges by avalanche effects that are attracted to the gate and stored there. This is called "Drain Avalanche Hot-Carrier Injection". That´s not very good for the gate oxide but in a PROM you do that only once.
https://www.richis-lab.de/ROM01.htm
:-/O
Noopy:
Well a BBD is also a memory, it´s an anlog memory.
The other BBDs can be found here: https://www.eevblog.com/forum/projects/different-die-pictures/msg3632153/#msg3632153 (and following)
And of course I have listed them here: https://www.richis-lab.de/bbd.htm
Now that should be a Matsushita/Panasonic MN3007. The MN3007 is the PMOS version of the MN3207 (https://www.richis-lab.de/bbd04.htm).
Surprise! That´s not a MN3007 but a MN3207!
Interesting they changed a MN3207 to a MN3007. The MN3207 is completely useless in a circuit designed for the MN3007. It would have been more economic to use any other DIL-8 chip and sell the MN3207 as it is.
Looking at the MN3207 (https://www.eevblog.com/forum/projects/different-die-pictures/msg3672253/#msg3672253) I just found five masks. With the better picture out of the counterfeit MN3007 we know can spot the sixth mask. It seems to be a via in the silicon oxide.
Here you can see the way the MN3207 went. The MN3207 has a pin 1 marking and some kind of a frame.
The MN3007 in the middle has just been ground a little. You can still see the pin 1 marking and the frame except in an area in the upper left corner. There are also some grinding marks.
The right MN3007 has been ground flat. They had to paint it and because of that the pins are black on their shoulders. You can spot grinding marks too.
https://www.richis-lab.de/bbd05.htm
:-/O
Noopy:
U552C built by VEB Mikroelektronik Karl Marx (what a name ;D). The U552C is a p-channel EPROM with 2kBit of memory. It is similar to the first EPROM 1702A built by Intel. RD should be the date code for December 1983.
Since the EPROM can be erased with UV light it has a window on top of the package. Here we see the version with a special ceramic window. They did a different version with a quartz glass window. The ceramic window needs nearly three times more light to erase the memory.
Since the U552 is a p-channel EPROM it needs 5V at Ucc and Ubb and -9V at Ugg and Udd to work properly. To write information into the memory you have to decrease Udd to -48V and increase Ubb to 13,2V (max voltages).
CS is chip select. PR makes it possible to write data. P1 and P2 are test inputs.
Udd and Ucc are connected with two bondwires. Ubb is not connected directly but the pin is connected to the area below the die. This special pin is tagged with an arrow on the package.
The die is 3,5mm x 3,2mm. The smallest structures are a little smaller than 10µm so it´s easy to identify and analyze the circuits.
Some markers to check the process quality.
There are five numbers. In GDR the masks were named with letters while numbers showed the revision. It looks like they had to modify one mask eight times! :-/O
And some test structures! :-+
This one looks like a normal MOSFET.
Here on the left side, there is another "normal" MOSFET. On the right side there is a MOSFET with a metal gate electrode. Sometimes such MOSFETs with a thick gate oxide are used for ESD protection.
Perhaps a MOSFET with a polysilicon gate but a thick gate oxide?
On the lower edge of the die there is a metal line connected to two testpads so you can check the conductivity of the metal layer.
Hey, some kind of a logo that is integrated in an active structure. :-+
The S-layer acts as gate electrode for the transistors left and right of the S.
At every input bondpad there is the complementary type of a grounded gate NMOS (ggNMOS). In this MOSFET a parasitic bipolar transistor is conducting whenever an ESD impulse occurs.
On the right side of the die there are two 32x32 memory arrays (white). The address inputs A0-A6 are converted in differential signals (blue). A0-A4 control the column selection between the two memory areas (green). The 2*32 lines are converted to 2*16 to 2*8 to 2*4 (cyan). The address inputs A5-A7 control these switches. The 8 output signals are fed into an inverter stage (orange). If the chip select circuit (pink) is active the inverter stage can control the push-pull output stages (yellow) O1-O6. If you want to write data additional transistors (red) bypass the output stage.
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