Miller charge vs gate charge - suitability of FETs for different applications

[incf]

So those HSP4048 MOSFETs have a large miller charge (18.5nC) compared to the charge needed to get the gate up to its threshold voltage, which is about 6nC. This makes it unsuitable for totem-pole applications without using significant negative gate drive voltages for the off-state, or using very slow switching speeds

I stumbled across a thread [1] online stating that the ratio of "miller charge" to gate charge can make a FET more or less suitable for certain applications.

Can anyone recommend an application note or similar that I can learn more about this from?

[1] https://www.reddit.com/r/AskElectronics/comments/13a9q33/comment/jj9yqfd/?utm_source=share&utm_medium=web3x&utm_name=web3xcss&utm_term=1&utm_content=share_button

[RoGeorge]

Usually FET means a junction FET, or JFET.  The one in the reddit thread is a MOSFET.  Another note, Miller is the name of a dude, so Miller capacitance, Miller charge, etc. should be spelled with capital M letter.

To make sense of the implications of Miller charge when switching a MOSFET, see if this video makes sense:

Miller Plateau effect within MOSFETs explained – a simple and intuitive approach
Biricha


The Miller capacitance (and implicitly Miller charge) is the one between GD, and during the MOSFET switching, it appears as if would be in parallel with the GS capacitance (C_GS is responsible for the gate charge).  Depending on how exactly a MOSFET is used, the ratio between the two parasitic capacitances may be more or less important.

If the above didn't clarify your question, you may want to read more about the Miller effect in general.  The next video tells in an intuitive way why the Miller effect happens (and how it can be circumvented in certain cases):

#207: Basics of a Cascode Amplifier and the Miller Effect
w2aew


Notice how the transistor here is a BJT.  The Miller capacitance affects an amplifier no matter the technology.  Can be a transistor, a tube, an opamp, etc.:  https://en.wikipedia.org/wiki/Miller_effect

[David Hess]

It means that when switching high voltages, the reverse transfer capacitance (between the gate and drain), dominates over the input capacitance (between gate and source).  FETs with low reverse transfer capacitance are more suited to fast high voltage applications.

[BadeBhaiya]

It means that when switching high voltages, the reverse transfer capacitance (between the gate and drain), dominates over the input capacitance (between gate and source).  FETs with low reverse transfer capacitance are more suited to fast high voltage applications.

Wouldn't NFETs with a high reverse transfer capacitance be more suitable for high side switching? Since the effect of miller charge are somewhat countered as long as the drain is connected to a low impedance current source (and hence maintains the voltage even when the MOSFET is on)

[David Hess]

It means that when switching high voltages, the reverse transfer capacitance (between the gate and drain), dominates over the input capacitance (between gate and source).  FETs with low reverse transfer capacitance are more suited to fast high voltage applications.

Wouldn't NFETs with a high reverse transfer capacitance be more suitable for high side switching? Since the effect of miller charge are somewhat countered as long as the drain is connected to a low impedance current source (and hence maintains the voltage even when the MOSFET is on)

If the drain voltage is changing, then it is still pumping charge into the gate.

[TimFox]

It means that when switching high voltages, the reverse transfer capacitance (between the gate and drain), dominates over the input capacitance (between gate and source).  FETs with low reverse transfer capacitance are more suited to fast high voltage applications.

Wouldn't NFETs with a high reverse transfer capacitance be more suitable for high side switching? Since the effect of miller charge are somewhat countered as long as the drain is connected to a low impedance current source (and hence maintains the voltage even when the MOSFET is on)

Current source loads are high impedance and allow the drain-gate voltage to swing, causing high current in the gate circuit through the Miller capacitance (drain to gate).

[mtwieg]

In the context of FETs for power electronics, the ratio often referred to is the ratio of miller charge Qgd to gate source charge Qgs. Keep in mind gate source charge Qgs and gate charge Qg (aka total gate charge) are very different things. Qgs is defined as the gate charge required to change Vgs from zero to the miller plateau voltage Vgp (usually a bit above Vth). Qg is much larger, it's the charge required to bring Vgs from zero to some specified voltage (often 10V).

Here's why this ratio is important in theory:
Consider an N-channel FET where are terminals are initially all at zero volts, so Vgs=0 and Vds=0. We'll also assume there isn't anything connected to the gate instead of FET's internal capacitances. Now let's force Vds to go high (near the rated VDSS of the FET). This will will cause charge Qgd to be injected into the gate capacitance (meaning the gate on the charge will be equal to Qgd of the FET). If this is greater than the Qgs of the FET,  then Vgs will rise to Vgp, and therefore the FET channel will conduct current. This causes switching losses to increase drastically, often leading to device failure.

I want to emphasize that Qgd>Qgs is a necessary condition for this parasitic turn-on to occur, but it is not a sufficient condition. Unlike the scenario above, we always connect some gate driver to the gates of the FET, and this circuit absorbs at least some of Qgd, reducing how much charge actually ends up on the gate. Whether this parasitic turn-on actually happens depends on factors aside from Qgd and Qgs, including:
1. The output voltage of the gate driver (a negative output drastically helps).
2. The source resistance of the gate driver (low is better).
3. The rate of change of the Vds transition (slower is better).
4. Gate and source inductance (lower is better, especially for high switching speeds).

Up until maybe 15-20 years ago, power MOSFETs which satisfied the Qgd<Qgs condition were actually pretty hard to come by. But that was typically not a problem because the rise/fall times of Vds were modest. But back then it was much rarer to see switching frequencies above 100kHz.

[incf]

Side question 1: About values being given as charges and not capacitance. I understand that charge is more useful for various reasons.

Do the "actual parasitic capacitor" values (eg. Cgs, Cgd) change with voltage? Or is the charge figure just a way to factor in the miller effect into the ratings?

[TimFox]

The semiconductor parasitic capacitances are voltage dependent, but the charge can be computed by integration for a given voltage swing.

[incf]

Side question 2: why are semiconductor capacitances voltage dependent? Is that some special property of doped silicon?

Side question 3: As an academic exercise, would placing an external capacitor from gate to source be a feasible way to make a FET exhibit the equivalent of Qgd<Qgs? (I guess there would be a small amount of inductance, maybe that wouldn't be guaranteed to work for very fast power FETs/switching circuits?)

My intuition says that if external capacitance is made sufficiently large that the visible effects/symptoms of the internal parasitic capacitances could be eliminated (eg. oscillation, miller plateau, etc.)

[mtwieg]

Side question 2: why are semiconductor capacitances voltage dependent? Is that some special property of doped silicon?

A full explanation would be very involved... I would look up varactors (a basic voltage-dependent capacitor) if you're interested in the basic mechanism.

Side question 3: As an academic exercise, would placing an external capacitor from gate to source be a feasible way to make a FET exhibit the equivalent of Qgd<Qgs? (I guess there would be a small amount of inductance, maybe that wouldn't be guaranteed to work for very fast power FETs/switching circuits?)

Yes adding extra Cgs is one way to prevent parasitic turn-on in some cases. But it's usually not the best method, so it's rarely seen.

[incf]

Oh, it's just the same mechanism as in silicon diodes like the 1N4148's reverse voltage vs capacitance curve. Up until this point I ascribed the capacitance to 'magic'

Side question 4: Does that nonlineariy apply to the gate oxide too? (if one were to somehow exclude the other parasitic capacitances) I'd think that the capacitance of the gate oxide layer would be fairly constant and that all of the voltage dependence might be in the parasitic structures?

[TimFox]

Reverse-biased PN junctions:  the thickness of the depletion region (dielectric) depends on the bias voltage (increased thickness and reduced capacitance at higher reverse voltage).
The oxide insulation is closer to a fixed capacitance, but to the source-drain channel and substrate.

[David Hess]

Side question 1: About values being given as charges and not capacitance. I understand that charge is more useful for various reasons.

Do the "actual parasitic capacitor" values (eg. Cgs, Cgd) change with voltage? Or is the charge figure just a way to factor in the miller effect into the ratings?

The capacitances do change with voltage, sometimes significantly, making charge a more useful specification.

Side question 2: why are semiconductor capacitances voltage dependent? Is that some special property of doped silicon?

The capacitance changes as the width of the depletion region changes.

Side question 4: Does that nonlineariy apply to the gate oxide too? (if one were to somehow exclude the other parasitic capacitances) I'd think that the capacitance of the gate oxide layer would be fairly constant and that all of the voltage dependence might be in the parasitic structures?

Gate oxide capacitance is very stable, but there is a variable width depletion region under it.

The capacitance change is very nonlinear, especially in the new Superjunction type of devices which have more going on.

https://www.vishay.com/docs/66864/an849.pdf

[MathWizard]

Sometimes I've seen MOSFET gates driven from a single, small signal diode, connected to an op-amp, and nothing else. Even in a power supply.

So how can they discharge the gate fast enough, with just the reverse leakage of a diode ?? Maybe such circuits are that slow, it doesn't matter much.

I should fire up the PSU and scope, and see what happens on a breadboard.

[David Hess]

Sometimes I've seen MOSFET gates driven from a single, small signal diode, connected to an op-amp, and nothing else. Even in a power supply.

So how can they discharge the gate fast enough, with just the reverse leakage of a diode ?? Maybe such circuits are that slow, it doesn't matter much.

I should fire up the PSU and scope, and see what happens on a breadboard.

Could it be a low voltage zener diode to prevent the gate from being pulled significantly below the threshold voltage?

Almost all operational amplifiers cannot drive a power MOSFET gate quickly anyway.

[Siwastaja]

Side question 3: As an academic exercise, would placing an external capacitor from gate to source be a feasible way to make a FET exhibit the equivalent of Qgd<Qgs? (I guess there would be a small amount of inductance, maybe that wouldn't be guaranteed to work for very fast power FETs/switching circuits?)

Sure you can - there is parasitic resistance and inductance from both MOSFET and the capacitor, though, so it's not as good as if the ratio was originally better within the MOSFET, but still very effective. But the big question is: why wouldn't you do the same with the gate driver itself? After all, you would be adding Cgs to sink the charge coming through Cgd. You can as well sink that by grounding the gate with a transistor - that's exactly what your already existing gate driver is doing anyway!

And that gate driver is the part people who say that Cgd must be smaller than Cgs to prevent parasitic turn-on are forgetting. Parasitic turn-on only happens if the gate driver is too weak (R of the gate driver's output transistor, plus your explicit Rg on your PCB, plus MOSFETs internal parasitic Rg, plus inductances of them all) to absorb the excess of that charge coming through Cgd.

Now some larger gate drivers (especially for IGBTs) have features like "Miller Clamp", which is basically just a copy of the output, with a low-side switch, with slightly modified timing, so that you can connect it directly to the MOSFET gate - what it essentially does is to bypass your explicit Rg, which you are using to control the slew rate of the bottom side switch, but which has the side effect of making the gate driver absorb less of the charge pulse coming through Cgd. With a separate "Miller clamp" pin, you can have both the slew rate control of external Rg, and the better sinking of externally injected charge during the time when the bottom side switch should stay firmly off.

Another way to achieve the same is negative gate drive voltage. Say, just switch to -5V instead of 0V, and now a few volts injected through Cgd is no big deal. But double-sided supplies are pain in the ass, requiring charge pumps or isolated supplies, level shifting of signals inside drivers, ...

In the end, Vgs is quite simple to measure on a prototype with an oscilloscope, so you easily get an idea how close to spurious turn-on you actually are.

[bson]

The gate 'capacitor' is charged/discharged at the gate.  The Miller 'capacitor' is charged by the drain.  With high voltages the latter dominates since it has to be charged to a higher voltage.