Author Topic: minimum load circuit for lab psu  (Read 5801 times)

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Offline nemail2Topic starter

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minimum load circuit for lab psu
« on: May 26, 2019, 10:17:27 pm »
Hi

in this: https://www.eevblog.com/forum/projects/how-to-wiregnd-everything-correctly-to-get-accurate-adc-readings-in-my-project/msg2439009/#msg2439009
project I'm looking for a solution to constantly draw about 6mA or so to have a minimum load which helps stabilize everything.

LM334 doesn't work out cause it only works down to about 1V when set to about 6mA
My currently used circuit (T8, D11, R25, R46) doesn't work quite well either and the zener diode gets really hot (above 75 °C).

The circuit in the attachment works, but it needs -5V which I don't have. I wanted to avoid adding additional switching noise by a, say TC7660 or something like that to generate the negative voltage.
Does anyone know of an off the shelf solution for this? The circuit in the screenshot works really nice even down to 0V.

Thanks!
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Offline Jay_Diddy_B

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Re: minimum load circuit for lab psu
« Reply #1 on: May 26, 2019, 10:53:39 pm »
Hi,

You can try a current mirror circuit like this:







This works well if the V2 is greater 100mV, which is pretty good.

The circuit will not work as well in practice because the two transistors are not at the same temperature. The temperature of Q1 is a function of the output voltage of the power supply.

I have attached the LTspice model.

Regards,
Jay_Diddy_B
 
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Offline NiHaoMike

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Re: minimum load circuit for lab psu
« Reply #2 on: May 26, 2019, 11:23:35 pm »
The classic electronic load circuit with an opamp and MOSFET would work nicely down to very close to 0V.
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Offline schmitt trigger

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Re: minimum load circuit for lab psu
« Reply #3 on: May 26, 2019, 11:58:25 pm »
For the current mirror that Jay_didy suggests, you may find low cost, dual matched pairs from both Nexperia and OnSemi.
Do a parametric search on their websites.
They should be more than enough for your requirements.

Of course, if you want to splurge and money is not an issue, then the MAT01 from Analog Devices is for you.
 
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Offline Jay_Diddy_B

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Re: minimum load circuit for lab psu
« Reply #4 on: May 27, 2019, 12:21:11 am »
Hi here is the model for the scheme proposed by NiHaoMike:





This depends on the op-amp working with the inputs near the -ve rail. Some op-amps work well like this others do not. Check the common mode range of the inputs and input bias currents etc.

I chose 60mV across the shunt to get away from input offset and input offset drift.

I have attached the model.

Regards,
Jay_Diddy_B
 
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Offline xavier60

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Re: minimum load circuit for lab psu
« Reply #5 on: May 27, 2019, 12:45:12 am »
This shows what I did for a Preload circuit. https://www.eevblog.com/forum/projects/linear-lab-power-supply/msg2388873/#msg2388873
I really don't think accuracy of the current is important, so long as the current path avoids the shunt.
I used a MOSFET in another design with no noticeable advantage.

EDIT: I should point out that below about 1V, the load becomes resistive.
The linked bench supply project does adjust down to 9mV output.
« Last Edit: May 27, 2019, 12:56:09 am by xavier60 »
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Offline Jay_Diddy_B

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Re: minimum load circuit for lab psu
« Reply #6 on: May 27, 2019, 12:56:06 am »
Hi this xavier60's circuit:





I have attached the model

Jay_Diddy_B
 
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Offline NiHaoMike

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Re: minimum load circuit for lab psu
« Reply #7 on: May 27, 2019, 03:20:01 am »
This depends on the op-amp working with the inputs near the -ve rail. Some op-amps work well like this others do not. Check the common mode range of the inputs and input bias currents etc.
Pretty much any general purpose opamp designed for single rail use, including the common LM358, works just fine with its inputs down to and even slightly below 0V. Getting close to the positive rail is where they typically start to misbehave. (Except for rail to rail opamps, of course.)

For simplicity, you could use a NPN transistor and a pullup resistor instead of the opamp, although that would make the load degenerate to a resistor below about 0.7V rather than much lower for the opamp solution.

Then there's PTC elements, of which the ones commonly found in old CRT TVs tend to work well with a cold resistance of just a few ohms. (That's probably a bit too much of a load for your use, however.)
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Offline nemail2Topic starter

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Re: minimum load circuit for lab psu
« Reply #8 on: May 27, 2019, 07:24:44 pm »
awesome, thanks for all your help! I'll take a closer look at the various solutions and will then let you know which I implemented in my Lab PSU!!
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Offline nemail2Topic starter

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Re: minimum load circuit for lab psu
« Reply #9 on: May 27, 2019, 07:36:03 pm »
another thing: what happens if the two NPN transistors in Jay_Diddy_B's circuit actually aren't a matched pair?

instead of xavier60's circuit I could just use a LM334 as well, as that works down to 1V as well.
I also do like the opamp solution, however if I could get away cheaper with just a resistor and two NPNs, that'd be nice :)


edit: what about this one? https://www.mouser.at/ProductDetail/Diodes-Incorporated/DMMT5551-7-F?qs=sGAEpiMZZMshyDBzk1%2FWi3NKRur4siPQ87U2jNAVT5E%3D
looks good :)
« Last Edit: May 27, 2019, 08:00:14 pm by nemail2 »
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Offline nemail2Topic starter

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Re: minimum load circuit for lab psu
« Reply #10 on: May 27, 2019, 10:45:46 pm »
Ok so i have kind of made a decision to go with the matched-pair npn solution.
That DMMT5551-7-F should be able to dissipate those 6-7mA @ 12.288V max output voltage at V_ADJ.

Any objections?

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Offline Jay_Diddy_B

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Re: minimum load circuit for lab psu
« Reply #11 on: May 27, 2019, 10:53:29 pm »
Hi,

We can look at the impact of temperature with this model:






The temperature of Q1 is stepped from 35C to 100C.

I have added the 47 Ohm emitter resistors to reduce the sensitivity.


The downside to the emitter resistors is that the circuit works above 300mV





Regards,

Jay_Diddy_B
« Last Edit: May 27, 2019, 10:56:35 pm by Jay_Diddy_B »
 
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Offline xavier60

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Re: minimum load circuit for lab psu
« Reply #12 on: May 28, 2019, 01:48:35 am »
With the added Emitter resistors, might cause some residual voltage at the output when CV is set to zero volts. It wouldn't be much.
Mine causes 9mV.
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Offline nemail2Topic starter

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Re: minimum load circuit for lab psu
« Reply #13 on: May 28, 2019, 06:16:45 am »
that does look good, doesn't it? 300mV is certainly better than what I'm having now. also more stable. and still cheaper/less parts than the opamp solution.

residual voltage at the output of the PSU itself? because of the drain? or because of the lack of a drain when set to 0mV where the load circuit isn't working?
sorry for the stupid question...
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Offline xavier60

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Re: minimum load circuit for lab psu
« Reply #14 on: May 28, 2019, 06:53:24 am »
that does look good, doesn't it? 300mV is certainly better than what I'm having now. also more stable. and still cheaper/less parts than the opamp solution.

residual voltage at the output of the PSU itself? because of the drain? or because of the lack of a drain when set to 0mV where the load circuit isn't working?
sorry for the stupid question...
With mine, the small Base bias current causes a small voltage drop across the Emitter resistor while the regulator is off. This small voltage is transferred to the output via the transistor.
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Offline nemail2Topic starter

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Re: minimum load circuit for lab psu
« Reply #15 on: May 28, 2019, 07:18:12 am »
that does look good, doesn't it? 300mV is certainly better than what I'm having now. also more stable. and still cheaper/less parts than the opamp solution.

residual voltage at the output of the PSU itself? because of the drain? or because of the lack of a drain when set to 0mV where the load circuit isn't working?
sorry for the stupid question...
With mine, the small Base bias current causes a small voltage drop across the Emitter resistor while the regulator is off. This small voltage is transferred to the output via the transistor.

let's say I have a short on the output, could that blow the ass out of the transistor? what about a diode to prevent current to flow in the wrong direction?
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Offline xavier60

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Re: minimum load circuit for lab psu
« Reply #16 on: May 28, 2019, 08:38:37 am »
that does look good, doesn't it? 300mV is certainly better than what I'm having now. also more stable. and still cheaper/less parts than the opamp solution.

residual voltage at the output of the PSU itself? because of the drain? or because of the lack of a drain when set to 0mV where the load circuit isn't working?
sorry for the stupid question...
With mine, the small Base bias current causes a small voltage drop across the Emitter resistor while the regulator is off. This small voltage is transferred to the output via the transistor.

let's say I have a short on the output, could that blow the ass out of the transistor? what about a diode to prevent current to flow in the wrong direction?
A short on the output shouldn't cause a problem.
Because I sometimes charge batteries, the last two bench supplies that I built are designed to briefly tolerate applied reverse polarity.
I use a diode and a polyswitch just to protect the preload circuit.
Not all regulator topologies can be made to tolerate applied reverse polarity such as those with voltage follower output stages.
« Last Edit: May 28, 2019, 10:57:41 am by xavier60 »
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Offline nemail2Topic starter

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Re: minimum load circuit for lab psu
« Reply #17 on: June 03, 2019, 09:25:02 pm »
what concerns me a bit after thinking a while about it (sorry for the late response, didn't have time to hobby around recently) is the negative current when the emitter resistors are in place which is shown in your diagram at voltages below 0.1V and also my spice simulation says the same thing.

also, I was thinking about using the BC847ALT1G for this, instead of the DMMT5551-7-F to reduce my BOM (and I have already bought the BC847ALT1G in high quantity (at least in regards of hobbyists use)). they should work as well, right? maximumoutput voltage is 20V. what about backfeed voltage of let's say motors or magnetic coils (relais) would they be an issue for the Vceo=45V of the BC847ALT1G? the DMMT5551-7-F has a much higher Vceo of 160V. not sure if that would even help though, when dealing with backfed voltage like that. i guess I'd need some other protection to mitigate this issue but that's for another topic...

thanks!
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Offline nemail2Topic starter

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Re: minimum load circuit for lab psu
« Reply #18 on: July 04, 2019, 06:27:39 am »
ok so i have built this up with the DMMT5551-7-F matched pair and without the emitter resistors. what should i say... the magic smoke escaped from the DMMT5551-7-F at about 7-8V output set voltage. so i bodged in the emitter resistors (48 Ohms) and replaced the DMMT5551-7-F. The magic smoke did not escape again but now i can't get my outout below 120mV. before those emitter ristors my output went down to 3mV.

Why is it so? LTSpice shows some negative current at the emittors, is it something to do with that?
As soon as I disconnect the current mirror, the voltage drops to normal (3-5mV).

What is going on there?

Thanks!
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Offline duak

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Re: minimum load circuit for lab psu
« Reply #19 on: July 04, 2019, 07:09:50 pm »
I think the output voltage no longer goes to zero because the current mirror is injecting current into +V_ADJ when the output voltage is << 600 mV.  The diode connected transistor T4a will develop a certain collector/base voltage as well as the voltage developed across its emitter resistor.  This will forward bias T4b's base emitter junction.  When +V_ADJ is lower than T4b's base voltage by a few hundred mV, T4b's base-collector junction will also start to conduct and allow current to flow into +V_ADJ.

Did you say that T4 was damaged without the emitter resistors?  What I think may have happened was that the thermal dissipation of T4b was exceeded due to thermal runaway.  Even though these devices are matched fairly well (the spec sheet says they are adjacent dice) T4b will be hotter than T4a when +V_ADJ is increased and when this happens its collector current will be greater than the reference current.  This increases its temperature which increases its collector current which increases its dissipation and so on...  Do you have the recomended heat sink area on the PCB?

I suggest reducing the value of the emitter resistor for T4a and measure T4b's emitter voltage to determine its emitter current and calculating the sinking current and its power dissipation at various output voltages.  You may also find that by reducing the emitter resistor value the current mirror will not inject current into the output.
« Last Edit: July 04, 2019, 11:58:51 pm by duak »
 
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Offline xavier60

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Re: minimum load circuit for lab psu
« Reply #20 on: July 04, 2019, 08:13:37 pm »
R1 needs to be 56K to reduce the residual voltage drop across R3 to about 10mV when the output is set to 0V.
Try 1.5K for R2.
A lower value for R3 would further reduce the residual voltage.
« Last Edit: July 04, 2019, 08:16:19 pm by xavier60 »
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Offline nemail2Topic starter

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Re: minimum load circuit for lab psu
« Reply #21 on: July 06, 2019, 12:20:11 pm »
I think the output voltage no longer goes to zero because the current mirror is injecting current into +V_ADJ when the output voltage is << 600 mV.  The diode connected transistor T4a will develop a certain collector/base voltage as well as the voltage developed across its emitter resistor.  This will forward bias T4b's base emitter junction.  When +V_ADJ is lower than T4b's base voltage by a few hundred mV, T4b's base-collector junction will also start to conduct and allow current to flow into +V_ADJ.

Did you say that T4 was damaged without the emitter resistors?  What I think may have happened was that the thermal dissipation of T4b was exceeded due to thermal runaway.  Even though these devices are matched fairly well (the spec sheet says they are adjacent dice) T4b will be hotter than T4a when +V_ADJ is increased and when this happens its collector current will be greater than the reference current.  This increases its temperature which increases its collector current which increases its dissipation and so on...  Do you have the recomended heat sink area on the PCB?

I suggest reducing the value of the emitter resistor for T4a and measure T4b's emitter voltage to determine its emitter current and calculating the sinking current and its power dissipation at various output voltages.  You may also find that by reducing the emitter resistor value the current mirror will not inject current into the output.

sounds reasonable. yes T4 was damaged without the emitter resistors, the magic smoke did escape.
There is quite some area on the PCB but I didn't check it with the datasheet. a friend however told me that he never saw a current mirror without the emitter resistors so i guess I'll just put them in.
I'll try to reduce the values and measure things. Thanks!
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Offline nemail2Topic starter

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Re: minimum load circuit for lab psu
« Reply #22 on: July 06, 2019, 12:21:38 pm »
R1 needs to be 56K to reduce the residual voltage drop across R3 to about 10mV when the output is set to 0V.
Try 1.5K for R2.
A lower value for R3 would further reduce the residual voltage.
I'm sorry, to which schematic are you referring with the part names?
Sounds very promising, though! Thanks!
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Offline xavier60

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Re: minimum load circuit for lab psu
« Reply #23 on: July 06, 2019, 03:35:53 pm »
R1 needs to be 56K to reduce the residual voltage drop across R3 to about 10mV when the output is set to 0V.
Try 1.5K for R2.
A lower value for R3 would further reduce the residual voltage.
I'm sorry, to which schematic are you referring with the part names?
Sounds very promising, though! Thanks!
I was using the references from Reply #11.
HP 54645A dso, Fluke 87V dmm,  Agilent U8002A psu,  FY6600 function gen,  Brymen BM857S, HAKKO FM-204, New! HAKKO FX-971.
 
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Offline nemail2Topic starter

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Re: minimum load circuit for lab psu
« Reply #24 on: July 06, 2019, 04:24:58 pm »
I was using the references from Reply #11.
OK thanks, will try it out!
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