Author Topic: minimum load circuit for lab psu  (Read 5798 times)

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Offline nemail2Topic starter

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Re: minimum load circuit for lab psu
« Reply #25 on: July 10, 2019, 01:10:54 am »
OK so first I tried 56k for R1 and 1.5k for R2 and R3. There was still voltage fed into the PSU and I was seeing about 60mV instead of 9-10mV. Certainly better but still not where I'd like it to be.
So I went up to 100k with R1 and down to 47 Ohm for R3 (keeping R2 at 1.5k). Output voltage fell to 20mV instead of 9-10mV and according to the 121GW meter no current was flowing via R1 into the PSU (before there was like a few dozens of µA flowing into the PSU). So I'm not sure whether the PSU isn't going down to 10mV because it is virtually unloaded or if the current mirror is still upping the voltage on the PSU output. Also, the current was increasing up to 2.5mA as I was increasing the output voltage of the PSU up to 16V. With the original values, the current stayed stable (at some 0.6mA).

I'm not sure how to overcome this. Is it even possible to make a circuit which works down to like 10 mV and stays stable all the way up to 16 V? I mean it would be OK if the circuit does not sink much current at very low voltages, it seems that my PSU is happy with very little amounts of current to stabilize in low output voltage regions.

The circuit which I was using in the previous revision (see attachement) with the zener diode basically did the business (after I added a series resistor to the zener it stopped heating up like crazy) but it is quite unstable so I'm having a hard time calibrating that additional current out in software. That thing varies in input voltage and with temperature but at least it brings my PSU down to the desired 9-10mV with ease...

I'd also be willing to buy some fancy chippy which can do the business for me, even for quite a price if it does a reasonable job. But I'm afraid, as often, this is nothing you can solve by simply throwing money on it...

Thanks for any advice!
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Offline duak

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Re: minimum load circuit for lab psu
« Reply #26 on: July 10, 2019, 03:01:13 am »
Three things to think about:

- a MOSFET current mirror,
- add a negative supply - it just needs a volt or two and a few milliamps.
- an incandescant light bulb - consider them to be PTC thermistors and have a wide range of resistance..  Try something like 24 V at 20 mA or even a small line operated one.


 
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Offline nemail2Topic starter

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Re: minimum load circuit for lab psu
« Reply #27 on: July 10, 2019, 03:18:20 am »
Three things to think about:

- a MOSFET current mirror,
- add a negative supply - it just needs a volt or two and a few milliamps.
- an incandescant light bulb - consider them to be PTC thermistors and have a wide range of resistance..  Try something like 24 V at 20 mA or even a small line operated one.

regarding the MOSFET current mirror i found this: http://tera.yonsei.ac.kr/class/2013_2_1/lecture/Lect_22%20MOSFET%20Current%20Mirror%20and%20Active%20Load.pdf
unfortunately this is way beyond my knowledge. I'll churn through it but I highly doubt that I'll get something useful out of it...

negative supply: where would i put that? are we talking about the npn current mirror?

incandescant light bulb: sounds like a 50's solution :-D and I can't imagine how that would work (again because of lacking knowledge) :-D
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Offline xavier60

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Re: minimum load circuit for lab psu
« Reply #28 on: July 10, 2019, 03:30:51 am »
The residual voltage should simply be due to R1's current flowing through R3 and it's voltage also appearing at the Collector.
First check what the real minimum regulated voltage is by checking what the CV op-amp is doing at minimum voltage setting.
My bench supply wants to regulate to 0V so the CV op-amp reacts by swinging its output hard low.
My other bench supply( 20A ) uses a MOSFET so there is no residual voltage applied to the output. When I set the regulation to 0V, I can accurately measure the 47 ohms across the output terminals.
« Last Edit: July 10, 2019, 07:59:24 am by xavier60 »
HP 54645A dso, Fluke 87V dmm,  Agilent U8002A psu,  FY6600 function gen,  Brymen BM857S, HAKKO FM-204, New! HAKKO FX-971.
 
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Offline nemail2Topic starter

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Re: minimum load circuit for lab psu
« Reply #29 on: July 10, 2019, 01:32:04 pm »
The residual voltage should simply be due to R1's current flowing through R3 and it's voltage also appearing at the Collector.
First check what the real minimum regulated voltage is by checking what the CV op-amp is doing at minimum voltage setting.
My bench supply wants to regulate to 0V so the CV op-amp reacts by swinging its output hard low.
My other bench supply( 20A ) uses a MOSFET so there is no residual voltage applied to the output. When I set the regulation to 0V, I can accurately measure the 47 ohms across the output terminals.

The CV op-amp is outputting 6mV when the PSU is set to 0mV. Just measured that.
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Offline nemail2Topic starter

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Re: minimum load circuit for lab psu
« Reply #30 on: July 10, 2019, 02:08:02 pm »
what about this? according to the simulation (lol) this works down to a few millivolts. i'll breadboard that!
i really don't care that it needs an opamp and an n-channel fet. i have already spent so much time on this that i'd gladly spend some bucks for a nice solution, especially if it is that stable!

simulation attached. rename LM358.txt into LM358.lib and put it in the directory where Draf4.asc is.
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Offline edavid

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Re: minimum load circuit for lab psu
« Reply #31 on: July 10, 2019, 03:19:26 pm »
what about this? according to the simulation (lol) this works down to a few millivolts. i'll breadboard that!
i really don't care that it needs an opamp and an n-channel fet. i have already spent so much time on this that i'd gladly spend some bucks for a nice solution, especially if it is that stable!

Go back and look at Jay's practical version of this circuit.

Also, have you considered using a JFET?  There isn't a great selection these days, but maybe a few MMBFJ202 in parallel?
 
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Offline nemail2Topic starter

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Re: minimum load circuit for lab psu
« Reply #32 on: July 10, 2019, 03:43:59 pm »
Go back and look at Jay's practical version of this circuit.

Also, have you considered using a JFET?  There isn't a great selection these days, but maybe a few MMBFJ202 in parallel?

lol completely forgot about that one. is there a particular reason for M1 being a Trench-FET in Jay's circuit?
i have breadboarded my version in the meantime and I'm quite happy. It really works good with a IRF3708 (had that one lying around) and a LM358. Sure, input offset and input offset drift got me with my circuit so the drawn current isn't exactly to the mA what I expected but near enough and certainly stable from 36mV output voltage up to 16V!
So I have to tune this and take things from Jay's circuit to make this practical.
Also I was going to measure the opamps output on the scope while tuning the voltage to see if tends to (or does) oscillate.

One concern I still have:
Given that my output voltage may start to oscillate at some point with some load (as I don't have proper electronic loads and most importantly don't know how to thorougly test a PSU) that constant minimal load may start to oscillate as well.
So I was thinking to make this thing quite slow so it doesn't oscillate to buggery if the output voltage goes bonkers. Would that be practical? Or is it just part of the curse? Is Jay's R4/C1 already doing the job?

Why a JFET and in what context? Why multiple of them in parallel? I only wanna sink a few mA at up to 16V (max.) :-)

Thanks!
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Offline edavid

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Re: minimum load circuit for lab psu
« Reply #33 on: July 10, 2019, 04:58:21 pm »
Is Jay's R4/C1 already doing the job?
Yes, that's their purpose.

Quote
Why a JFET and in what context?
One component current sink that goes down to 0V.

Quote
Why multiple of them in parallel?
1. To make IDSS selection easier if you don't have a quantity of parts to pick through.
2. If using SOT23 parts, to spread the power dissipation.

Quote
I only wanna sink a few mA at up to 16V (max.) :-)
In that case one SOT23 package should be OK, if you can find the right one.
 
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Offline duak

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Re: minimum load circuit for lab psu
« Reply #34 on: July 10, 2019, 05:09:28 pm »
An incandescent bulb has a lower resistance when it is cold vs when it is hot.  (see attachment)  This is not a constant current sink but it does draw more current at low voltages than at high voltages, a function that your circuit requires.  It does not introduce offset voltages and it does work down to zero volts.  It was used by Bill Hewlett of Hewlett-Packard for their first variable frequency oscillator to stabilize the output voltage in 1940.  It does seem like a 50s solution, but it could be the simplest solution.  I used it to solve a residual voltage problem on a DC power supply.

MOSFETs could be substituted for the bipolar transistors in the present current mirror.  This would eliminate any current injection into the output.  The devices should be matched and tested to ensure that the sink current is actually what is expected.

Connecting the emitters of the current mirror to a small negative voltage of -1 V relative to AGND would ensure that the output voltage would be zero when needed.  There were some threads on this forum recently on this subject but I can't seem to find them quickly.  TI and other manufacturers make some devices for this.

There are a number of ways to test a power supply for stability.  I would start with using power resistors of differing values for loads and try varying the voltages and currents applied while monitoring the output. I would then use a function generator to inject a low level 10 Hz square wave into IC2A-2 while repeating the above tests.  If the output does not overshoot or ring, then it is basically stable. 
 
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Offline nemail2Topic starter

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Re: minimum load circuit for lab psu
« Reply #35 on: July 10, 2019, 05:16:49 pm »
One component current sink that goes down to 0V.

you got my attention. like this, only with a jfet?
https://www.eevblog.com/forum/projects/minimum-load-circuit-for-lab-psu/?action=dlattach;attach=747333

the mosfet/opamp solution has the advantage that it behaves quite predictable and stable so i can remove the minimum load current from the display in software quite easy...
how about those properties with the one-component JFET current sink?
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Offline nemail2Topic starter

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Re: minimum load circuit for lab psu
« Reply #36 on: July 10, 2019, 05:28:38 pm »
An incandescent bulb has a lower resistance when it is cold vs when it is hot.  (see attachment)  This is not a constant current sink but it does draw more current at low voltages than at high voltages, a function that your circuit requires.  It does not introduce offset voltages and it does work down to zero volts.  It was used by Bill Hewlett of Hewlett-Packard for their first variable frequency oscillator to stabilize the output voltage in 1940.  It does seem like a 50s solution, but it could be the simplest solution.  I used it to solve a residual voltage problem on a DC power supply.
Thank you very much, I'm always interested in cool history lessions like that (really!). Awesome solution and I'll definitely keep that in mind. For this project though, where I'm trying to make the PSU as precise as possible (without spending thousands of bucks, though), that seems a bit too unpredictable.

MOSFETs could be substituted for the bipolar transistors in the present current mirror.  This would eliminate any current injection into the output.  The devices should be matched and tested to ensure that the sink current is actually what is expected.
I'll take a look whether there are matched MOSFETs in one case being sold, I don't really want to match them by hand, to be honest. I might try and breadboard that but I'm kinda sold for the opamp solution already, I have to admit. In my design there is a spare opamp (of a dual package) anyway since I have ditched that sense input idea and I have a suitable MOSFET in my BOM as well already. So, meeh.. :-)

Connecting the emitters of the current mirror to a small negative voltage of -1 V relative to AGND would ensure that the output voltage would be zero when needed.  There were some threads on this forum recently on this subject but I can't seem to find them quickly.  TI and other manufacturers make some devices for this.
I'd be really interested in those devices. I wasn't really able to find anything besides the LM334 but that does only work from about 1V upwards. I tried to connect -5V out of a TC7660 to the negative pin of the LM334 to shift everything but that didn't work either. Something was drawing current but it was not the LM334. I had my Lab PSU set to Imax of 100mA and those were drawn so I guess that was BS, what I breadboarded there.

There are a number of ways to test a power supply for stability.  I would start with using power resistors of differing values for loads and try varying the voltages and currents applied while monitoring the output. I would then use a function generator to inject a low level 10 Hz square wave into IC2A-2 while repeating the above tests.  If the output does not overshoot or ring, then it is basically stable.
I have a cheap load from aliexpress which i already used to torture my PSU, so far so good, no issues. Injecting some signal is something I didn't do yet. What amplitude should that square wave have and what current capability?
I was planning to build up an array of mosfets with some power resistors and some atmega to be able to connect and disconnect various resistors very fast and thus change load very fast without switch contact bouncing and look with a scope what the output does.
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Offline edavid

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Re: minimum load circuit for lab psu
« Reply #37 on: July 10, 2019, 05:29:26 pm »
One component current sink that goes down to 0V.

you got my attention. like this, only with a jfet?
https://www.eevblog.com/forum/projects/minimum-load-circuit-for-lab-psu/?action=dlattach;attach=747333

No, see attached.  I didn't bother trying to dig up a J202 model.  It's resistive below VP, don't know if that's OK...

 
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Offline duak

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Re: minimum load circuit for lab psu
« Reply #38 on: July 10, 2019, 11:17:19 pm »
For transient response testing I would try a 22K resistor in series with a 100n cap applied to IC2A-2.   For small signal response I would set the function generator to 25 mVp-p square wave.  You should see about 50 to 100 mVp-p on the output.  100 Hz may be too high because of the 100 uF capacitors on the output so you can reduce the frequency.   You can then increase the function generator output signal.  You should then see the rise and fall times change the waveform into more of a triangle or ramp.  Depending on the load and current limit setting, at some point it may invoke current limiting and you should see the supply change to constant current mode.  The transition should be clean without weird spikes or oscillations.
 
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Offline nemail2Topic starter

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Re: minimum load circuit for lab psu
« Reply #39 on: July 11, 2019, 05:00:51 am »
I'll try to get or make a function gen somewhere and eventually I'll do those tests for sure, thanks for going to detail :-)
Here is the revised version 1.9 of my Lab PSU, still have to fix all the designators, though:
https://github.com/mamama1/LabPSU_Darlington

I have implemented the opamp + n-fet current sink and tuned it to about 6mA. I also inserted a pin header so I'll be able to measure the current which the circuit is sinking with my multimeter so I can calibrate it out in the software. I guess it will vary from build to build due to manufacturer tolerance of the resistors, opamp and fet.
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Offline xavier60

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Re: minimum load circuit for lab psu
« Reply #40 on: July 11, 2019, 07:36:48 am »
Was it possible to avoid having the preload current flow through the CS resistor?
HP 54645A dso, Fluke 87V dmm,  Agilent U8002A psu,  FY6600 function gen,  Brymen BM857S, HAKKO FM-204, New! HAKKO FX-971.
 


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