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minimum load circuit for lab psu

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nemail2:
what about this? according to the simulation (lol) this works down to a few millivolts. i'll breadboard that!
i really don't care that it needs an opamp and an n-channel fet. i have already spent so much time on this that i'd gladly spend some bucks for a nice solution, especially if it is that stable!

simulation attached. rename LM358.txt into LM358.lib and put it in the directory where Draf4.asc is.

edavid:

--- Quote from: nemail2 on July 10, 2019, 02:08:02 pm ---what about this? according to the simulation (lol) this works down to a few millivolts. i'll breadboard that!
i really don't care that it needs an opamp and an n-channel fet. i have already spent so much time on this that i'd gladly spend some bucks for a nice solution, especially if it is that stable!

--- End quote ---

Go back and look at Jay's practical version of this circuit.

Also, have you considered using a JFET?  There isn't a great selection these days, but maybe a few MMBFJ202 in parallel?

nemail2:

--- Quote from: edavid on July 10, 2019, 03:19:26 pm ---Go back and look at Jay's practical version of this circuit.

Also, have you considered using a JFET?  There isn't a great selection these days, but maybe a few MMBFJ202 in parallel?

--- End quote ---

lol completely forgot about that one. is there a particular reason for M1 being a Trench-FET in Jay's circuit?
i have breadboarded my version in the meantime and I'm quite happy. It really works good with a IRF3708 (had that one lying around) and a LM358. Sure, input offset and input offset drift got me with my circuit so the drawn current isn't exactly to the mA what I expected but near enough and certainly stable from 36mV output voltage up to 16V!
So I have to tune this and take things from Jay's circuit to make this practical.
Also I was going to measure the opamps output on the scope while tuning the voltage to see if tends to (or does) oscillate.

One concern I still have:
Given that my output voltage may start to oscillate at some point with some load (as I don't have proper electronic loads and most importantly don't know how to thorougly test a PSU) that constant minimal load may start to oscillate as well.
So I was thinking to make this thing quite slow so it doesn't oscillate to buggery if the output voltage goes bonkers. Would that be practical? Or is it just part of the curse? Is Jay's R4/C1 already doing the job?

Why a JFET and in what context? Why multiple of them in parallel? I only wanna sink a few mA at up to 16V (max.) :-)

Thanks!

edavid:

--- Quote from: nemail2 on July 10, 2019, 03:43:59 pm ---Is Jay's R4/C1 already doing the job?

--- End quote ---
Yes, that's their purpose.


--- Quote ---Why a JFET and in what context?

--- End quote ---
One component current sink that goes down to 0V.


--- Quote ---Why multiple of them in parallel?

--- End quote ---
1. To make IDSS selection easier if you don't have a quantity of parts to pick through.
2. If using SOT23 parts, to spread the power dissipation.


--- Quote ---I only wanna sink a few mA at up to 16V (max.) :-)

--- End quote ---
In that case one SOT23 package should be OK, if you can find the right one.

duak:
An incandescent bulb has a lower resistance when it is cold vs when it is hot.  (see attachment)  This is not a constant current sink but it does draw more current at low voltages than at high voltages, a function that your circuit requires.  It does not introduce offset voltages and it does work down to zero volts.  It was used by Bill Hewlett of Hewlett-Packard for their first variable frequency oscillator to stabilize the output voltage in 1940.  It does seem like a 50s solution, but it could be the simplest solution.  I used it to solve a residual voltage problem on a DC power supply.

MOSFETs could be substituted for the bipolar transistors in the present current mirror.  This would eliminate any current injection into the output.  The devices should be matched and tested to ensure that the sink current is actually what is expected.

Connecting the emitters of the current mirror to a small negative voltage of -1 V relative to AGND would ensure that the output voltage would be zero when needed.  There were some threads on this forum recently on this subject but I can't seem to find them quickly.  TI and other manufacturers make some devices for this.

There are a number of ways to test a power supply for stability.  I would start with using power resistors of differing values for loads and try varying the voltages and currents applied while monitoring the output. I would then use a function generator to inject a low level 10 Hz square wave into IC2A-2 while repeating the above tests.  If the output does not overshoot or ring, then it is basically stable. 

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