Simple 10MHz to 25MHz frequency multiplier

[tom66]

I'm looking for a frequency multiplication solution;

Either: 10MHz to 25MHz directly (2.5x frac-N PLL?) or 10MHz to 50MHz with a divide by two option. If possible, it would be also nice to be able to set the multiplication on demand (I2C/SPI), though this is not critical for my application. Also, jitter isn't a major concern.

What I've found so far is GHz+ RF ICs. I'm unsure if these will work down to 10~50MHz.

[dannyf]

The simplest and cheapest is to get one of those STM32F chips and program it to use outside oscillator (from your source), program a 2.5x multiplier, and turn on the mco pin.

DDS chips would also work as well.

[Rerouter]

An AD9850 acting in a PLL would do the job, but its serial loading, not i2c or spi (they even show you how to do it in the datasheet)

[fcb]

Another (old school) way to do it.

Make sure you have a square-wave, then filter the 5th harmonic and apply to a divider.

[dannyf]

then filter the 5th harmonic

How would you design the cut off frequencies for an input signal of 10M - 50Mhz?

[jpb]

You've not said what you want to do with it, but if you're looking for a 25MHz clock output then this chip

ON SEMICONDUCTOR - NB3N502DG - PLL CLOCK MULTIPLIER, 8SOIC

(which is £2:51 + VAT from Farnell) will do a 2.5 multiply directly (one of the examples they give in the data sheet is 10MHz input with 25MHz output with S0 and S1 both set to 1):

http://www.farnell.com/datasheets/699220.pdf

http://uk.farnell.com/on-semiconductor/nb3n502dg/pll-clock-multiplier-8soic/dp/2101849

[tom66]

What I'm looking to do is to use a 10MHz reference input from a Rubidium source to generate a 25MHz clock for an AD9837.

Yes I could use another DDS to generate it, and/or various tricks for picking up on the harmonic. Or a microcontroller purely for the clock. It surprises me though that there's no "drop in" solution for a simple, low frequency multiplier. Is it just not that common of an engineering problem? It's obviously not impossible to do - the fact that every powerful MCU includes one is proof of this.

edit: jpb, did not see your post. Looks like exactly what I'd need. Thanks! I take back the "rare" part as above.

[Hugoneus]

edit: jpb, did not see your post. Looks like exactly what I'd need. Thanks! I take back the "rare" part as above.

I had a quick look at that part and I couldn't find where the bandwidth of the PLL was mentioned. I don't even see a loop filter in the block diagram. I assume this means that the bandwidth of the PLL is as high as possible, in which case it would be a good thing since with such a low multiplication factor, there is no way the VCO can ever beat the phase noise of your reference.

[branadic]

You could use a CDCE913 for that job.

[dannyf]

Or a microcontroller purely for the clock.

And you can use the spi / i2c module in a mcu to adjust the multiplier ratio, etc.

There are various PLL chips (TI for example has a whole family of those chips) that does that. OnSemi has / had some as well (as I recall, they were from Sanyo that On bought, FS63xx). Cirrus also has some chips - those guys are fairly big in timing.

What you want are fractional PLL.

[hlavac]

How about some old school 74HC4046A plus a little bit of jelly bean logic (counter for divide by 5, 74hc74 for divide by two...) or  74HC4059 programmable divider?

[fcb]

What I'm looking to do is to use a 10MHz reference input from a Rubidium source to generate a 25MHz clock for an AD9837.

I just had peak at the d/s for this part. It looks like it max's out at 16MHz.

My thought was to change your design so that you could use the 10MHz ref directly.

[dannyf]

74HC4046A

Would it work at 50Mhz? and hopefully with some headroom too?

Probably not.

[jpb]

edit: jpb, did not see your post. Looks like exactly what I'd need. Thanks! I take back the "rare" part as above.

I had a quick look at that part and I couldn't find where the bandwidth of the PLL was mentioned. I don't even see a loop filter in the block diagram. I assume this means that the bandwidth of the PLL is as high as possible, in which case it would be a good thing since with such a low multiplication factor, there is no way the VCO can ever beat the phase noise of your reference.

I'm not sure if this answers your question but the input bandwidth is 5-27MHz for crystals and 2-50MHz for clocks, there is a divide by P before the phase detector and a divide by M for the VCO but the maximum output frequency is 190MHz so you can't scale 50MHz by 4. Looking at the allowed multipliers they come in pairs that multiply to 10 so 2 and 5 or 3 and 3 1/3 or 4 and 2 1/2 but I'm not sure how that translates to P and M values.

[grumpydoc]

Would it work at 50Mhz? and hopefully with some headroom too?

Probably not.

Not at 50MHz - there is a variant which does 38MHz.

That would be adequate for 10MHz->25MHz though - divide the 10MHz by 2, and the 25MHz by 5 to get 5MHz and phase compare the two for the drive to the VCO.

[ConKbot]

then filter the 5th harmonic

How would you design the cut off frequencies for an input signal of 10M - 50Mhz?

25 MHz crystal and then an amp on the output? Seems goofy to use a the crystal as a filter instead of just a source, but, it would have the stability of the original 10 MHz signal, and as long as the 25 MHz crstal isnt too far off from nominal, then the desired harmonic should pass just fine.

[fcb]

Other options.

1. 74LS628 will run at 25MHz, they are a tad better than 4046 running free.
2. 25MHz VCXO, then discipline (PLL) this with your 10MHz (someone suggested 10MHz/2 to get 5MHz).
3. 50MHz VCXO as above but with /2 to get nicer square wave.

All of these (and others) will work - but you need to understand the phase noise they will introduce.

Can you tell us more about what your end-goal is, that typically results in other good suggestions.

[richard.cs]

25 MHz crystal and then an amp on the output? Seems goofy to use a the crystal as a filter instead of just a source, but, it would have the stability of the original 10 MHz signal, and as long as the 25 MHz crstal isnt too far off from nominal, then the desired harmonic should pass just fine.

For some reason this appeals to me. I think I like the simplicity, and if necessary you could deliberately de-Q the crystal a bit to widen the tuning. :-)

[analogcircuithacker]

Drive the reference input of an AD9913 DDS IC with your 10 MHz signal.
Program the clock multiplier to be its max value of 25 so the internal clock runs at 250 MHz.
Then program the output frequency to 25 MHz and you have 10 points per cycle.

Enjoy!

[edavid]

I don't understand why people are still suggesting ideas that are more expensive and more complicated than the NB3N502DG.  That just seems perfect.

[fcb]

+1
That's a great little part edavid.  I've just ordered a couple from Farnell for my toys draw.

[macboy]

I don't understand why people are still suggesting ideas that are more expensive and more complicated than the NB3N502DG.  That just seems perfect.

I agree. And there are many equivalent alternatives like ICS511, and others.