MOSFET gate connection length - ringing?

[Circlotron]

I'm just starting to draw up a physical variation of a board I have done many times before. This time, for reasons of trying to fit it into an existing box I have to split the thing into two boards; one with the PWM controller IC and the other contains the power stuff.

What it is is a SG3525 controller that drives a pair of mosfets in two side by side boost converters. The outputs are joined by a diode with a common cathode.  Input range is 10-15 volts, output is 16 volts 10 amps.  It's about as sophisticated as a steam locomotive, so let's not get sidetracked on that issue - it all works well enough for the intended application and has done so for many years and hundreds of examples.

So... depending on how I lay it out I may have mosfet gate leads from the SG3525 on one board to the mosfets on the other board as much as 2 inches long. The switching rate is 22.5kHz. Gate voltage rise is 100nS to plateau, 80nS plateau, 80nS to 10 volts. I understand the importance of the ground reference point location for the gate drive.

Is there much likelihood that this two inch length of wire connected to the gates will ring excessively? Should I put say 10K from gate to source right at the mosfets?

[tautech]

http://www.onsemi.com/pub_link/Collateral/SG3525A-D.PDF

Fig 12 shows a current limiting resistor from the supply to VCC, likewise in Fig 11 with gate resistors as well.

As it's quite normal to use low value gate resistors when driving FET's I'd look at chopping some in.

This other datasheet is as much use as the one above. 
http://www.st.com/content/ccc/resource/technical/document/datasheet/c0/12/98/4a/3b/1a/4b/8b/CD00000958.pdf/files/CD00000958.pdf/jcr:content/translations/en.CD00000958.pdf

[T3sl4co1l]

a. Don't worry about it. SG3525 is about as fast as as a sleeping donkey.  In related news, don't go more than about 100kHz switching frequency or else switching losses, and you should have no trouble "minimizing" loop inductance (but you can always optimize it instead, and control the reactive power with snubbers, and win a few more points efficiency in the process).  Provide additional grounds around the gate drive pins, and maybe double those up as well.

b. Extend the drivers to the switch board.  Put gate drivers (e.g. TC4427, if VCC is under 18V) right at the transistors, so that the board-to-board connection only needs to carry signal levels, no current spikes.  (In related news, expect to need to optimize loop inductance.)

Local drivers also work well when paralleling many transistors.  But because they will all switch at slightly different moments (due to differences in driver t_PLH and t_PHL, and transistor Qg and Vgs(th)), the switching loop components (diode/opposing transistor, supply bypass, loop L, parallel C, snubbers) need to be arranged in pairs at each position.  The result is much like stacking many single-cylinder engines in line: you get more power, with each unit being modular and well optimized, but you don't get any other advantages, like reduced ripple (which you get from an interleaved controller, which at this point, is very easily introduced, so it's not all bad conceptually).

Tim

[David Hess]

The SG3525 outputs will be faster when driving a transmission line instead of a close capacitive gate load but 2 inches should not be a problem.

I would put a low value series resistor near the gate of each MOSFET and adjust the value for minimum ringing.

[Circlotron]

http://www.onsemi.com/pub_link/Collateral/SG3525A-D.PDF

Fig 12 shows a current limiting resistor from the supply to VCC, likewise in Fig 11 with gate resistors as well.

As it's quite normal to use low value gate resistors when driving FET's I'd look at chopping some in.

Re fig 12, I do have a 12R resistor in place. That softens the upstroke but does nothing for the downstroke, although in fact it is fairly similar. Might have an experiment with an existing board and see how much R it will tolerate. I am using BUK761R3-30E mosfets and they have an input capacitance of almost 9000pF so keeping the switching frequency low helps keep the internal dissipation in the '3525 lower. Have plenty of boost inductance up my sleeve.

[Circlotron]

I would put a low value series resistor near the gate of each MOSFET and adjust the value for minimum ringing.

For the sake of experiment I can tack an uncut 1/4 W resistor mid air on an existing board to make the connection. Will the fact that the resistance is in the middle of the wire rather than at the mosfet end make much of a difference? Will it only damp the wire leading up to the resistance?

[T3sl4co1l]

FYI, you can calculate the RLC parameters of the drive circuit, and do a simple sanity check on whether it's reasonable or not, and to see what minimum Rg you need.

For inductance, assuming the path has a transmission line impedance in the 50-150 ohm range (less if you use lots of wide traces and parallel pins), then since that's about half of Zo (377 ohms), inductivity is about half of mu_0, or ~0.6 uH/m.

That's inductance per linear length of path.  So, say 3 inches (0.075m), 45nH.  More or less.

Gate capacitance.  You need the total equivalent, not the zero-bias figure.  That parameter low-balls the equivalent by around 4x.  Take Qg / Vg(on) = Cg(eq).  Qg is Qg(tot), preferably the max spec.  Vg(on) is the value Qg is measured at.

Suppose Qg is 50nC at 10V.  That gives Cg(eq) = 5nF.

Impedance.  This is nothing more than sqrt(L/C) = Z.  The ratio of inductance to capacitance, works precisely the same as the ratio of voltage to current (I mean, give or take a square or root), and has units of ohms.

If Lstray = 45nH and Cg = 5nF, then 45/5 = 9, and sqrt(9) is 3.  So, 3 ohms.

Pick Rg > Z.  Equal gives critical damping; over gives extra damping (~RC characteristic).

Note you also want Rg on the order of the driver's output capacity, i.e., R ~ (VCC / Ipk).  Like for the SG3525 (0.5A peak max.) at 12V, you'd use around 6 ohms.  (Less than 3 ohms won't really do anything -- the driving pin will be driving the gate nearly directly at that point.  More will significantly reduce the load on the driver, which slows things down.  Slow may be desirable for EMI.)

In either case, pick the greater of the two options.

Naturally, L and C also define a characteristic time constant, or cutoff frequency.  The frequency is F = 1 / (2*pi*sqrt(L*C)), and the time (1/4 wave) is t = pi*sqrt(L*C)/2.

For this example, the time is 23ns.  Against a typical 50ns fall time of the SG3525, you won't have to worry about Lstray or Rg this low.

If the risetime of your driver is already slower than the 1/4 wave time, then choosing Rg ~= Z will have little to no effect on actual speed.  If you want to slow it down further, you'll need to use that many times more Rg to have an impact.

I'm guessing something around 10-50 ohms would be best, or if you want to go for speed, use the local-driver design, and whatever Rg is suitable then (maybe 1-10 ohms).

Tim

Edit: helps if I use consistent numbers

[tautech]

http://www.onsemi.com/pub_link/Collateral/SG3525A-D.PDF

Fig 12 shows a current limiting resistor from the supply to VCC, likewise in Fig 11 with gate resistors as well.

As it's quite normal to use low value gate resistors when driving FET's I'd look at chopping some in.

Re fig 12, I do have a 12R resistor in place. That softens the upstroke but does nothing for the downstroke, although in fact it is fairly similar. Might have an experiment with an existing board and see how much R it will tolerate. I am using BUK761R3-30E mosfets and they have an input capacitance of almost 9000pF so keeping the switching frequency low helps keep the internal dissipation in the '3525 lower. Have plenty of boost inductance up my sleeve.

http://cache.nxp.com/documents/data_sheet/BUK761R3-30E.pdf?pspll=1
QG(tot) total gate charge ID = 25 A; VDS = 24 V; VGS = 10 V =  154 - nC

That's one shite load of total gate capacitance. 
Pull down resistors needed too?

[T3sl4co1l]

Holy shit, 153nC!  Wait, you've fallen into that trap, haven't you...

1.3 milliohms? 

For a 10A converter?  Split into two channels?  Maaan!

You're way past the point of switching loss versus conduction loss, there.  Especially for a feeble driver like this!

Run the numbers on switching loss, and compare that with conduction loss.  Choose a new transistor based on the tradeoff.

For switching loss, assume the transition time is triangular, so the transistor burns peak watts of Vpk * Ipk.  The triangle base width is t_r or t_f, so the energy is (1/2)*t_r*Vpk*Ipk, and the average switching power is that times Fsw.

Which means the equivalent switching loss resistance is this power divided by Ipk^2, or Fsw*t_r*Vpk / (2*Ipk).  Which is actually 2.1mohm (assuming 100kHz switching frequency, 50ns transition time, 17V peak switch voltage, and 20A peak switch current), which isn't really all that far off.  But if you have two channels, then current divides and you'll have 4mohm each, which is what the Rds(on)'s should be similar to.

Note that this equivalent resistance is proportional to transition time, which will be proportionally slower for a bigger transistor.  Probably more like 200ns in this case, so that the comparison is even more unfavorable (24mohm Rsw vs. 1mohm Rcond).  And as you choose more optimal transistors, this figure will fall, while Rds(on) rises, so that they meet in the middle, but not at a proportional midpoint, but more like the geometric average (so, instead of using a 25-times higher Rds(on), maybe try only a 5-times higher Rds(on)).

BTW, if you did want to push this circuit for maximum efficiency -- by using an external gate driver IC -- it's not clear that that transistor would offer much advantage.  It's spec'd with a 5 ohm driver resistance.  It might go faster with a stiffer driver, but it's not clear how much.  In other words, internal (gate spreading) resistance may be on the order of 1-2 ohms, which sounds horrible for such a massive transistor, but it's not uncommon, as these super-low resistance FETs are most often used in low frequency switching and DC applications (like ideal-OR power circuits).

Tim

[David Hess]

I would put a low value series resistor near the gate of each MOSFET and adjust the value for minimum ringing.

For the sake of experiment I can tack an uncut 1/4 W resistor mid air on an existing board to make the connection. Will the fact that the resistance is in the middle of the wire rather than at the mosfet end make much of a difference? Will it only damp the wire leading up to the resistance?

It will work fine as a test but in the final layout, there are two reasons that I would add this resistor close to the gate; 1 - It will absorb any overshoot generated by the remote driver and 2 - it will prevent negative resistance oscillation of the transistor itself as it passes through its active region.

Neither are commonly a problem and even less so when the driver is located close but it is always something that I worry about and adding the spot for the resistor to the layout is cheap.  I know I am paranoid but am I paranoid enough?

[lukaq]

That fet is just about as wrong as you can go for such low power converter

[T3sl4co1l]

Neither are commonly a problem and even less so when the driver is located close but it is always something that I worry about and adding the spot for the resistor to the layout is cheap.  I know I am paranoid but am I paranoid enough?

I would suspect, yes.  At the frequencies where a MOSFET is likely to oscillate (10-100MHz), the connecting trace (if it's under, say, 0.3 m length) still looks like a lumped inductance.  So only the loop properties are important, i.e. that the RLC series circuit is overdamped.  So it shouldn't matter where the R is, even if it's integrated into the driver itself.

(To be fair, the driver output of a CMOS driver (e.g. TC4420) will have a little capacitance as well, in parallel with its Rds(on) output resistance.  But that's almost always less than Cg(eq) of the transistor being driven, so that shouldn't modify things, really.)

I once made a high speed driver (t_r < 5ns) with about 10cm of connection length (pretty wide connections, but still, the nH's add up).  No gate resistor.  First try, the switching was okay, but there was a ~60MHz squiggly (which corresponds to loop inductance plus something or another capacitance in there...) during turn-on.  I added a ferrite bead around the transistor gate.  Squiggly gone!  Nice smooth rise, no more RF tone-burst, a little bit of overshoot.  The ferrite bead saturates during the brunt of the gate-drive edge, so the rise/fall time isn't seriously impaired, just delayed a few ns.  It does, however, get kind of hot, on account of being saturated every 2MHz...

Tim