BJT between OP and FET? - Adjustable Constant Current Load

[MRAWESOME]

Ahoy.
I am planning out a build of an adjustable, constant current load to test all sorts of circuits. Dave's design in EEVblog #102() simply connects the output of the opamp to the gate of the FET. However, this design uses a BJT between the output of the OP and the gate of the FET: https://www.eevblog.com/forum/projects/project-high-power-constant-current-programmable-load/msg117559/#msg117559

I am wondering why? My first guess is that the gate charge is 'dealt with' more easily by the BJT than by the OP. This would make adjustments quicker and so would then make the circuit more stable(?).

Is my guess correct?

[dannyf]

Stability I suspect.

Being essentially a capacitor, power fets are difficult to drive, especially for high speed opamps.

[zlymex]

It is about the stability/overshot and how fast the current follows the setting. It is not necesarry to use a BJT if you don't mind the speed. Various method of compensation can be used to solve the stability problem. Here is the screen shot that I fiddle with those parameters in the hope to achieve the largest phase margin(>100 degree). I added an 10nF capacitor to the FET make things worse.

[diyaudio]

It is about the stability/overshot and how fast the current follows the setting. It is not necesarry to use a BJT if you don't mind the speed. Various method of compensation can be used to solve the stability problem. Here is the screen shot that I fiddle with those parameters in the hope to achieve the largest phase margin(>100 degree). I added an 10nF capacitor to the FET make things worse.

Interesting analysis, have you taken into consideration the parasitic capacitance components at the at Gate, Source and Drain? @JDaddy has made some similar interesting findings as well.  Is it really even necessary to add the pole/zero at the component level (it seems so obfuscated doing it that way)  why not introduce it around error amplifier.

[zlymex]

It is about the stability/overshot and how fast the current follows the setting. It is not necesarry to use a BJT if you don't mind the speed. Various method of compensation can be used to solve the stability problem. Here is the screen shot that I fiddle with those parameters in the hope to achieve the largest phase margin(>100 degree). I added an 10nF capacitor to the FET make things worse.

Interesting analysis, have you taken into consideration the parasitic capacitance components at the at Gate, Source and Drain? @JDaddy has made some similar interesting findings as well.  Is it really even necessary to add the pole/zero at the component level (it seems so obfuscated doing it that way)  why not introduce it around error amplifier.

The software I use is Tina 9, there are models build-in for components, therefore those capacitors of a MOSFET are already taken into account when I made the analysis. I added those pole/zero around the error amplifier in order to achieve the largest phase margin for the current source. This is necessary when the load changes such as inductive loads.