Mixed signal PCB layout help

[calvingloster]

Yes one of the output (red wires) to the piezo actuator is ground and I have not shown the power and ground connection to the amplifier PCB but those are connected with wires as well. This is for a scanning tunneling microscope. Very similar to the design here https://dberard.com/home-built-stm/. The frequency the piezo actuator is low, a few hundreds of Hz if I'm lucky enough to get that.

[temperance]

100MHz SPI is indeed quite tricky. Make sure your master/slave chips can handle it, then route the traces somewhat impedance controlled (no need to pay PCB manufacturer premium for this, but use an online calculator for rough approximation, important parameters are trace width and distance to the ground plane (prepreg thickness)). Then approximate the driving CMOS Rds_on, something like 20-30 ohms, and add explicit series R right at the output pin (MOSI, SCK, nCS at master, MISO at slave) to match the transmission line impedance, e.g. for a 70-ohm line a 33-47R would be right. You might need to test on prototypes because the driver R is an unknown parameter (and it will vary with temperature, sadly).

Another option to avoid having to terminate would be minimization of distance, place the SPI devices very close together, like an inch or so.

Or just use series termination with resistors at the driver side of things. Anything between 22...56R will do.

[jkostb]

Be very careful with split analog and digital ground planes. Usually it creates more issues (EMC emission violation). Usually you can solve this also by proper component placement and using 1 ground plane and careful trace routing. You should be very suspicious if datasheet or application notes recommends split ground planes. I made several designs where I ignored the recommendation of the datasheet/application note to use split planes. Never had noise issues or EMI issues. I have however seen designs failing EMI testing because they used split planes.

[uer166]

Just say no to split GND planes. Separate the analog/digital stuff (but keep it on the same plane). The advice for plane separation has been propagated from old and outdated mis-understandings of how noise actually couples between circuits.

There are a few applications where split GND  planes do help as was mentioned (low frequency, high current next to low-level measurements), but in 99% of cases you're simply creating an EMC issue out of nothing via dipole radiation, and not actually improving noise coupling whatsoever.

[gnuarm]

Be very careful with split analog and digital ground planes. Usually it creates more issues (EMC emission violation). Usually you can solve this also by proper component placement and using 1 ground plane and careful trace routing. You should be very suspicious if datasheet or application notes recommends split ground planes. I made several designs where I ignored the recommendation of the datasheet/application note to use split planes. Never had noise issues or EMI issues. I have however seen designs failing EMI testing because they used split planes.

Sure, you can screw up any design.  Your anecdotal accounts are not evidence of the appropriateness of splitting ground planes.

I don't know the current level of the piezo drives, but that is the sort of thing that using a split ground plane will work to reduce if not eliminate. 

[uer166]

gnuarm, you've been given many references (see above linked data by Rick Hartley and others). Other people have also explained the exact reasons and background regarding plane splitting that you seem to ignore.

The concepts are far from anecdotal, and can be simulated, measured, and tested..

[Siwastaja]

gnuarm, you've been given many references (see above linked data by Rick Hartley and others). Other people have also explained the exact reasons and background regarding plane splitting that you seem to ignore.

The concepts are far from anecdotal, and can be simulated, measured, and tested..

gnuarm is seemingly stuck with some concepts popular in appnotes and even among many EMC gurus in 1990's/early 2000's.

In reality, GND plane splits are really only useful for high accuracy DC-to-low-frequency circuits, and power planes do not magically offer zero inductance and full plane capacitance at device pin. All modern day EMC experts I have talked with recommend avoiding split planes (and instead think about split placement), and also emphasize the importance of local bypass capacitors at device pins, in which case a power plane offers nothing more compared to a wide power track. You still have to come from the plane through via, through thermal relief, to the pin, which adds almost as much inductance as a 0402 capacitor footprint.

[gnuarm]

gnuarm, you've been given many references (see above linked data by Rick Hartley and others). Other people have also explained the exact reasons and background regarding plane splitting that you seem to ignore.

The concepts are far from anecdotal, and can be simulated, measured, and tested..

And I have given details of why these approaches work.  I can't give you a reference, unless you want to buy one of his books or take the course like I did.

https://www.google.com/search?client=firefox-b-1-d&q=lee+ritchey+books

Everything Lee Ritchey taught, was analyzed in theory, simulation and tested on a physical circuit.  One of the more surprising results was the debunking of the idea that the "loop impedance" of a capacitor between the ground/power planes makes a difference to the effect on the chips.  This is a myth that persists because, "it sounds right".  However, the power/ground planes form a transmission line, supplying current until the wave reaches the capacitor.  The "loop impedance" is meaningless in this context, because of the distributed capacitance. 

People often apply the wrong theory.

[jkostb]

I have done my home work and studied books, notes, application notes from authors like Henry Ott, Kenneth Wyatt, Eric bogatin an many more authors. They all say the same: don't use split reference planes. This matches with my experience. My anecdotec stories are based on experience in past and based on literature from welknown experts in the field.

[gnuarm]

gnuarm, you've been given many references (see above linked data by Rick Hartley and others). Other people have also explained the exact reasons and background regarding plane splitting that you seem to ignore.

The concepts are far from anecdotal, and can be simulated, measured, and tested..

gnuarm is seemingly stuck with some concepts popular in appnotes and even among many EMC gurus in 1990's/early 2000's.

In reality, GND plane splits are really only useful for high accuracy DC-to-low-frequency circuits, and power planes do not magically offer zero inductance and full plane capacitance at device pin. All modern day EMC experts I have talked with recommend avoiding split planes (and instead think about split placement), and also emphasize the importance of local bypass capacitors at device pins, in which case a power plane offers nothing more compared to a wide power track. You still have to come from the plane through via, through thermal relief, to the pin, which adds almost as much inductance as a 0402 capacitor footprint.

Yes, many people continue to teach the "local" bypass capacitor theory, which has been solidly debunked.  Well, unless by "local" you mean within an inch or two. 

The idea that the high frequency capacitance of power/ground planes is of no value compared to traces for power is only valid when your circuit is not sensitive to high frequencies.  It is very common for circuits to be over designed in this regard.  The idea of "one capacitor for each power pin" was from the days when power/ground planes were not used and persisted in designs where power/ground planes are used.  Now we know better.   Well, some of us.

I assume you've looked at the impedance curve for caps, no?  At higher frequencies the inductance takes over and the impedance rises, making the cap pointless for decoupling.  This is where you need ground/power planes. If your chips do not have high current spikes on the power rails, this will not be important.  But most people have no idea how to even verify this. 

[gnuarm]

gnuarm, you've been given many references (see above linked data by Rick Hartley and others). Other people have also explained the exact reasons and background regarding plane splitting that you seem to ignore.

The concepts are far from anecdotal, and can be simulated, measured, and tested..

gnuarm is seemingly stuck with some concepts popular in appnotes and even among many EMC gurus in 1990's/early 2000's.

In reality, GND plane splits are really only useful for high accuracy DC-to-low-frequency circuits, and power planes do not magically offer zero inductance and full plane capacitance at device pin.

I like that you continue to talk about split planes only being useful in the exact situation the OP is seeing. 

[gnuarm]

I have done my home work and studied books, notes, application notes from authors like Henry Ott, Kenneth Wyatt, Eric bogatin an many more authors. They all say the same: don't use split reference planes. This matches with my experience. My anecdotec stories are based on experience in past and based on literature from welknown experts in the field.

What are your anecdotes on when split planes did not work?

[jkostb]

Hello Gnuarm,

Regarding your statement:
>I don't know the current level of the piezo drives, but that is the sort of thing that using a split ground plane will work to reduce if >not eliminate

It is not OK to give such advice to other engineers without having seen schematics, PCB layout or having detailed knowledge of the project. The big problem with split ground planes is that there is no return path for signals if they cross the split ground plane. Preferred return path is always the reference plane (e.g. ground plane), because this is the path of minimum inductance. If you split the ground plane, then return current must find other path. The result is a large loop antenna which radiates. This is the reason why I have seen so many projects fail radiated emission tests during EMC tests. If you use split planes, it is very difficult to prevent routing signals over split planes. So be very careful with giving other engineers wrong advice

[gnuarm]

Hello Gnuarm,

Regarding your statement:
>I don't know the current level of the piezo drives, but that is the sort of thing that using a split ground plane will work to reduce if >not eliminate

It is not OK to give such advice to other engineers without having seen schematics, PCB layout or having detailed knowledge of the project. The big problem with split ground planes is that there is no return path for signals if they cross the split ground plane. Preferred return path is always the reference plane (e.g. ground plane), because this is the path of minimum inductance. If you split the ground plane, then return current must find other path. The result is a large loop antenna which radiates. This is the reason why I have seen so many projects fail radiated emission tests during EMC tests. If you use split planes, it is very difficult to prevent routing signals over split planes. So be very careful with giving other engineers wrong advice

If you split off the ground plane of a sensitive analog circuit, with a connection to the digital ground plane at a specific point that will minimize the impact of digital ground noise to the sensitive analog circuit, where would the digital traces be running that they cross this split, other than at the point of connection???

You are making your own demons to fight off. 

Doctor, doctor, it hurts when I do that!  Then don't do that!

[jkostb]

> If you split off the ground plane of a sensitive analog circuit, with a connection to the digital ground plane at a specific point that will

So you  agree that you need some connection? But this is not a split ground plane right? A split ground plane has no interconnection right?
It is good to see that you start making progress learning  this topic. Now you need to learn that in many designs where you have multiple analog to digital converters it is usually not practical during PCB layout to make 1 small connection between analog and digital plan and route all signals over this small connection. So you start increasing the small interconnection, but then what is the difference with using continuous plane? Your theory is outdated, and it looks like you have done a lot of "theoretical" studies without any practical experience regarding this topic.

[gnuarm]

> If you split off the ground plane of a sensitive analog circuit, with a connection to the digital ground plane at a specific point that will

So you  agree that you need some connection? But this is not a split ground plane right? A split ground plane has no interconnection right?
It is good to see that you start making progress learning  this topic. Now you need to learn that in many designs where you have multiple analog to digital converters it is usually not practical during PCB layout to make 1 small connection between analog and digital plan and route all signals over this small connection. So you start increasing the small interconnection, but then what is the difference with using continuous plane? Your theory is outdated, and it looks like you have done a lot of "theoretical" studies without any practical experience regarding this topic.

I'm not going to banter back and forth forever.  Please read my posts.  I have always been talking about ground planes, split everywhere but for one point, where they are connected in a way, that prevents digital ground currents from entering the analog circuitry and disrupting sensitive circuitry.

What high speed digital signals will you be routing to the analog circuit???  You seem to want to create problems, rather than designing a simple circuit. 

Read my posts.  It's all there.  If you contort what I write, you will never understand. 

[Siwastaja]

Well, unless by "local" you mean within an inch or two.

Closer than that - millimeters, really, if at all possible. That's how I can see basically all existing circuit boards designed, local bypassing of all power pins that matter.

I assume you've looked at the impedance curve for caps, no?  At higher frequencies the inductance takes over and the impedance rises, making the cap pointless for decoupling.  This is where you need ground/power planes.

Inductance is no magic, power planes are no magic, and capacitors are no magic. Parasitic inductance is simply caused by distance. Capacitors are just "power planes" tightly coupled in a small package with very high dielectric constant and minimized distance between the planes for maximum capacitance - and minimum inductance. If a capacitor is placed 2mm away from the device pin it is bypassing, it does no worse than power plane 2mm away from the device pin. You can build a small-value but physically large distributed capacitor from power/gnd planes, but the capacitance will be small, whereas local bypassing with largest value of C in smallest possible package - something like 1uF in 0402 - does the same, plus the impedance curve extends to LF way better.

You can calculate low Z for a power/gnd plane pair modelled as a transmission line until cows come home, but you can't connect that inches wide transmission line into a device pin, so it does not matter. The connection to device pin (plus the via to the plane) is the bottleneck, and as a result, power plane gives very little of that low-ESL capacitance, just some picofarads. More capacitance is further away, after more inductance.

Power planes do no harm in itself, but if they give you false sense of security of not requiring proper bypass caps, then they do hurt. Also if they increase your layer count, then they hurt in your pockets.

[gnuarm]

Well, unless by "local" you mean within an inch or two.

Closer than that - millimeters, really, if at all possible. That's how I can see basically all existing circuit boards designed, local bypassing of all power pins that matter.

Oh, yes!  This is a superstition that is very hard to break.  I do it myself!  It doesn't prove anything.  I carry an amulet to prevent attacks by rampaging elephants.  Works a charm!

I assume you've looked at the impedance curve for caps, no?  At higher frequencies the inductance takes over and the impedance rises, making the cap pointless for decoupling.  This is where you need ground/power planes.

Inductance is no magic, power planes are no magic, and capacitors are no magic. Parasitic inductance is simply caused by distance. Capacitors are just "power planes" tightly coupled in a small package with very high dielectric constant and minimized distance between the planes for maximum capacitance - and minimum inductance. If a capacitor is placed 2mm away from the device pin it is bypassing, it does no worse than power plane 2mm away from the device pin. You can build a small-value but physically large distributed capacitor from power/gnd planes, but the capacitance will be small, whereas local bypassing with largest value of C in smallest possible package - something like 1uF in 0402 - does the same, plus the impedance curve extends to LF way better.

Clearly, you don't understand anything I've said.  The problem is that at frequencies above the SRF, the impedance across a capacitor rises until it is no longer useful for bypassing... at all!  The capacitance of the power/ground planes is small, but is effective all the way into the GHz region.  So when your bypass caps poop out, the power planes still do the job. 

Why does the small capacitance value of the planes not matter?  Because you need much less capacitance at high frequencies.  You should understand this.  I don't know why you continue to argue the point.  But maybe you don't understand.  You say, "local bypassing with largest value of C in smallest possible package - something like 1uF in 0402 - does the same".  But this is not true, which you would know if you ever looked that the impedance vs. frequency curve of the caps you use for bypassing.  Have you?

You can calculate low Z for a power/gnd plane pair modelled as a transmission line until cows come home, but you can't connect that inches wide transmission line into a device pin, so it does not matter. The connection to device pin (plus the via to the plane) is the bottleneck, and as a result, power plane gives very little of that low-ESL capacitance, just some picofarads. More capacitance is further away, after more inductance.

Power planes do no harm in itself, but if they give you false sense of security of not requiring proper bypass caps, then they do hurt. Also if they increase your layer count, then they hurt in your pockets.

You wag your tongue fiercely, but you have never actually tested your ideas.  Your hand waving of connecting the power plane to the pin being a bottle neck is not based on any technical analysis.  You clearly fail to understand the nature of a transmission line.  You are doing the same faulty sort of thinking that makes people talk about the loop impedance of a cap connected to a chip via the ground/power planes. 

As I've said, these are not my ideas.  This is from Lee Ritchey, who analyzed this in theory (correct theory), simulated it in a 3d field solver and tested it by building a board.  He connected the cap next to the pin, and at several distances from the pin.  There was virtually no difference in the voltage waveform at the pin, until the cap was something like 4 or 6 inches from the pin.  A very clear and simple demonstration.

If you want to argue about this, perhaps you should take it up with Lee Ritchey.  He is one of the very few "experts" who actually build circuits to verify his thinking.  It took me a while to get my head wrapped around what he was saying in his class.  Once I did, it all made sense.  People tend to get some wrong perspective on problems like this, and let it take them in all directions. 

[uer166]

gnuarm, you've been given many references (see above linked data by Rick Hartley and others). Other people have also explained the exact reasons and background regarding plane splitting that you seem to ignore.

The concepts are far from anecdotal, and can be simulated, measured, and tested..

And I have given details of why these approaches work.  I can't give you a reference, unless you want to buy one of his books or take the course like I did.

https://www.google.com/search?client=firefox-b-1-d&q=lee+ritchey+books

Everything Lee Ritchey taught, was analyzed in theory, simulation and tested on a physical circuit.  One of the more surprising results was the debunking of the idea that the "loop impedance" of a capacitor between the ground/power planes makes a difference to the effect on the chips.  This is a myth that persists because, "it sounds right".  However, the power/ground planes form a transmission line, supplying current until the wave reaches the capacitor.  The "loop impedance" is meaningless in this context, because of the distributed capacitance. 

People often apply the wrong theory.

Here is what Lee Ritchey has to say about splitting ground planes:

"Sometimes there is confusion as to the need for a separate analog ground and digital ground when a mixed technology
part, such as an A/D converter or read channel, is being used. This is not necessary, nor is it advisable. Once the reason
for having two different terminals is understood, it can be seen that two different grounds are not needed."

Not only are you using appeal to authority to push a mis-understood concept, but the authority itself disagrees with you.

[gnuarm]

gnuarm, you've been given many references (see above linked data by Rick Hartley and others). Other people have also explained the exact reasons and background regarding plane splitting that you seem to ignore.

The concepts are far from anecdotal, and can be simulated, measured, and tested..

And I have given details of why these approaches work.  I can't give you a reference, unless you want to buy one of his books or take the course like I did.

https://www.google.com/search?client=firefox-b-1-d&q=lee+ritchey+books

Everything Lee Ritchey taught, was analyzed in theory, simulation and tested on a physical circuit.  One of the more surprising results was the debunking of the idea that the "loop impedance" of a capacitor between the ground/power planes makes a difference to the effect on the chips.  This is a myth that persists because, "it sounds right".  However, the power/ground planes form a transmission line, supplying current until the wave reaches the capacitor.  The "loop impedance" is meaningless in this context, because of the distributed capacitance. 

People often apply the wrong theory.

Here is what Lee Ritchey has to say about splitting ground planes:

"Sometimes there is confusion as to the need for a separate analog ground and digital ground when a mixed technology
part, such as an A/D converter or read channel, is being used. This is not necessary, nor is it advisable. Once the reason
for having two different terminals is understood, it can be seen that two different grounds are not needed."

Not only are you using appeal to authority to push a mis-understood concept, but the authority itself disagrees with you.

Again, you misunderstand what is being said.  Lee is clearly talking about having distinct ground planes.  I've never said that was a good idea.

By explaining this again, I'm just  repeating myself.  If you want clarification, please read my prior posts, with an open mind, but most important, paying attention to what I say, not what you think I'm saying.  There is a big difference, which your post makes clear, you don't understand.

OK?  Can you do that?  Read what I wrote, not what you read!

[jkostb]

You keep referencing Lee Ritchie. I have read literature from Lee Ritchie and also seen lectures given by him. What you are posting on this forum, is NOT what he is teaching. Your theory about decoupling and bypass capacitors is ridiculous. Yes, the interplane capacitance is important for power integrity for modern high speed processors. But that does not mean you can get rid of the bypass capacitors. There is nothing magical regarding interplane or by pass capacitors and by simple physics laws you can prove that bypass capacitors are required.

It seems that you can not be convinced. That is OK. But what is not OK, is that you are teaching other engineers the wrong things. If you are so convinced about your theories, can you share some designs of high speed circuit boards which went into production ncluding layout? Can you also share EMI test results of these boards?

[Siwastaja]

Can you also share EMI test results of these boards?

The complexity of subject and pass/fail nature of qualifications make this futile. Obviously disastrously bad practices (for example: wiring GND with 10mil traces without bypass caps) get wed out, but stuff like believing in magic of power planes usually isn't bad enough to cause design to get rejected. One similar thing is paralleling of multiple different values of MLCCs. It's a really bad idea and thank god pretty much abandoned as the word gets out, but still some believe in it because they think they have evidenced it being helpful (while it truly isn't). Longer explanation here: https://www.eevblog.com/forum/projects/decoupling-caps-value/msg4891286/#msg4891286

Similarly, if GND plane splits are made with care and correctly, adding to placement separation and not substituting it, and avoiding crossing signals over the split, it might well pass the EMI, being only slightly worse, or in some specific case, actually better. But for a good rule of thumb, avoiding splits for HF and EMI, and using splits for low-frequency high-accuracy single-ended analog signals, is a good idea.

[gnuarm]

You keep referencing Lee Ritchie. I have read literature from Lee Ritchie and also seen lectures given by him. What you are posting on this forum, is NOT what he is teaching.

What I am saying here, is directly from his class and book (he only had one at the time).  I was very surprised by this, having heard the same religious garbage as everyone else.  Lee directly attacked the idea of considering the "loop inductance" because it means nothing.  The power/ground planes are not an inductive loop.  They are a transmission line with distributed inductance and capacitance. 

Consider a 50 ohm transmission line, with a 50 ohm resistive load and a very low impedance driver.  The initial wave will be at the driver voltage, with the corresponding current, at the very instant the driver output rises!  There's no delay, because the transmission line delivers the current to/from the driver the entire time the wave is propagating. 

In our case, the impedance is much lower, and the load is a capacitor, which continues to supply current when the wave reaches it.  So while the wave is propagating the transmission line distributed capacitance supplies the current.  When the wave reaches the capacitor, that supplies the current.  Notice there's no mention of distance.  Current flows from the instant the driver changes voltage all through the spike.

Your theory about decoupling and bypass capacitors is ridiculous. Yes, the interplane capacitance is important for power integrity for modern high speed processors. But that does not mean you can get rid of the bypass capacitors. There is nothing magical regarding interplane or by pass capacitors and by simple physics laws you can prove that bypass capacitors are required.

Why do people continue to misstate what I write???  I'm tired of the BS, I'm calling you on this!  Please find where I said bypass capacitors are not needed. 

It seems that you can not be convinced. That is OK. But what is not OK, is that you are teaching other engineers the wrong things. If you are so convinced about your theories, can you share some designs of high speed circuit boards which went into production ncluding layout? Can you also share EMI test results of these boards?

You know I can't share boards I have designed in my work.  They are property of my customers.  But I can say, not one has ever had a problem with EMI.  NEVER!

Before  you challenge someone, perhaps you should actually read what they write?

[lucy.sierra]

Just want to mention that Ken Wyatt will do an AMA so you can actually ask him his opinion.