Author Topic: Modern equivalent of 74HC4046 PLL?  (Read 4976 times)

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Offline Miti

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Modern equivalent of 74HC4046 PLL?
« on: April 15, 2020, 10:31:41 pm »
I hope you're all doing well,

I'm looking for a PLL/VCO chip that can extract the pixel clock from the horizontal sync pulses. The pixel clock is 21MHz, the horizontal sync is around 15KHz.
I tried HC4046 and used this calculator for the passives:

https://www.changpuak.ch/electronics/calc_03.php

It is very jittery and it only reaches 21MHz with C1 out of specs, <40pF when it needs to be >40pF. I suspect 15KHz is a bit low and the VCO is pushed to the limits.
The divider is in an FPGA and that part works well.

Do you know any simple chip that can do that?

Thanks!
« Last Edit: April 15, 2020, 10:33:26 pm by Miti »
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Offline Karel

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Re: Modern equivalent of 74HC4046 PLL?
« Reply #1 on: April 16, 2020, 07:28:52 am »
Never use that chip, use the Nexperia 74HCT9046 instead. It's much more stable.

https://assets.nexperia.com/documents/data-sheet/74HCT9046A.pdf
 

Offline jpb

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Re: Modern equivalent of 74HC4046 PLL?
« Reply #2 on: April 16, 2020, 08:28:05 am »
This application note might be relevant:
https://www.ti.com/lit/an/scaa088/scaa088.pdf
It is audio but at similar frequencies going from a few 10s of KHz to 10s of MHz.
The 4046 is only used for its phase detector while another chip is used for the PLL.
« Last Edit: April 16, 2020, 08:31:53 am by jpb »
 

Online Kleinstein

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Re: Modern equivalent of 74HC4046 PLL?
« Reply #3 on: April 16, 2020, 12:08:57 pm »
For slightly higher speed there is a 74LV4046.
 

Offline Miti

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Re: Modern equivalent of 74HC4046 PLL?
« Reply #4 on: April 18, 2020, 12:54:41 pm »
Thanks for your replies and I apologise for my slow response. I was busy with... life.

@ Karel
Yes, I read somewhere that 4046 is crap. I used TI HC404AM because it is specified at 3.3V but I guess I need 5V to make it work at 21MHz. Or at least get the least crappiness out of it.

@jpb
Nice and clean solution but it is quite expensive and it needs I2C and a pullable 21MHz crystal. Unfortunately Digikey doesn't carry any 21MHz crystal.

@Kleinstein
I'm trying to find a 3.3V device first.

Technically I only need a VCO that can do 21MHz, I can implement the phase and frequency comparator inside the FPGA.
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Offline NiHaoMike

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Re: Modern equivalent of 74HC4046 PLL?
« Reply #5 on: April 18, 2020, 02:15:39 pm »
What are the capabilities of the PLLs built into the FPGA?
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Online SiliconWizard

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Re: Modern equivalent of 74HC4046 PLL?
« Reply #6 on: April 18, 2020, 03:04:36 pm »
What are the capabilities of the PLLs built into the FPGA?

Yes, I had focused on the 4046 in my thoughts and just noticed that the OP was actually using an FPGA. Could be worth seeing if the embedded PLL(s) could do the job indeed. Thing is, with such a low input frequency, I highly doubt it would fit the specs of any FPGA's PLL... From what I remember, the min input frequencies are usually in the order of a few MHz?

I haven't taken a deep look, but the OP could take a look at Silab's offering: https://www.silabs.com/timing/clock-generators
maybe something appropriate there.

Edit: something still available and that looks like a possible fit: https://www.idt.com/document/dst/9173b-datasheet
typical "Genlock" PLL.
« Last Edit: April 18, 2020, 04:18:31 pm by SiliconWizard »
 

Offline jpb

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Re: Modern equivalent of 74HC4046 PLL?
« Reply #7 on: April 18, 2020, 04:29:54 pm »
Thanks for your replies and I apologise for my slow response. I was busy with... life.

@jpb
Nice and clean solution but it is quite expensive and it needs I2C and a pullable 21MHz crystal. Unfortunately Digikey doesn't carry any 21MHz crystal.

Technically I only need a VCO that can do 21MHz, I can implement the phase and frequency comparator inside the FPGA.
I see your point about 21MHz - it seems a rather awkward frequency. There are some stand alone oscillators.

Even going up to 42MHz (which could be followed by a divide by 2) it falls at the edge of two - both of which are quite expensive :
38MHz - 42MHz
https://www.digikey.co.uk/product-detail/en/crystek-corporation/CVCO55CL-0038-0042/CVCO55CL-0038-0042-ND/4356641
or
42MHz - 46MHz
https://www.digikey.co.uk/product-detail/en/crystek-corporation/CVCO55CL-0042-0046/744-1164-ND/1644079
going up to 84MHz with a divide by 4 and there is one centred on 85MHz but that is getting a bit silly:
https://www.digikey.co.uk/products/en/crystals-oscillators-resonators/vcos-voltage-controlled-oscillators/173?k=&pkeyword=&sv=0&pv640=291304&sf=0&FV=-8%7C173&quantity=&ColumnSort=0&page=1&pageSize=25
 

Offline Miti

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Re: Modern equivalent of 74HC4046 PLL?
« Reply #8 on: April 18, 2020, 07:58:30 pm »
What are the capabilities of the PLLs built into the FPGA?

15KHz is too low for the FPGA PLL. Cyclone 2 minimum PLL clock frequency is 10MHz, Cyclone 4 is 5MHz.
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Offline Miti

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Re: Modern equivalent of 74HC4046 PLL?
« Reply #9 on: April 18, 2020, 08:07:19 pm »
Edit: something still available and that looks like a possible fit: https://www.idt.com/document/dst/9173b-datasheet
typical "Genlock" PLL.

SiliconWizard you are a ...wizard  :-+
That IC is exactly what I was looking for. Actually after a google search for "Video Genlock", I found that ICS9173B (01, 15) is identical to MK9173-01, MK9173-15.
This answers my question in another post, this one https://www.eevblog.com/forum/projects/part-identification-236714/ , where I'm trying to identify a part marked HX73-15 or so I thought. In fact it is MK73-15 (which translates into MK9173-15) but the low resolution picture made it look like HX or HK.

Thank you sir!
Cheers!
« Last Edit: April 18, 2020, 08:10:38 pm by Miti »
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Offline Miti

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Re: Modern equivalent of 74HC4046 PLL?
« Reply #10 on: May 08, 2020, 11:42:28 pm »
Ok, so I bought this chip MK9173-15 from Ebay, US seller, good communication, all seems legit  :blah:. It kind of works. I input ~15KHz and it outputs 21MHz. The jitter however is horrible but the LCD module doesn't seem to care.
Is this expected from a genlock chip like this or is it because I bought from Ebay?
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Offline Zoli

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Re: Modern equivalent of 74HC4046 PLL?
« Reply #11 on: May 09, 2020, 05:50:31 am »
...
The jitter however is horrible but the LCD module doesn't seem to care.
...
Because you have a good "eye pattern"?
/ducks
I mean, the HF(21MHz) signal statistically is "cleanly" centered over the referece(15kHz) falling edge.
Of course, it would be nice to have a clean, jitterfree 21 MHZ, but I think, as long as the display doesn't care, why should you?
/hides
 
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Offline Miti

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Re: Modern equivalent of 74HC4046 PLL?
« Reply #12 on: May 09, 2020, 05:34:19 pm »
Of course, it would be nice to have a clean, jitterfree 21 MHZ, but I think, as long as the display doesn't care, why should you?

Well, the input to this circuit is the video output of an HP8591E spectrum analyzer that I want to up-convert to 1024x768 VGA. I wonder how sampling would be affected by the jitter. I have 95ns to sample the pixel so if I don't have a clock right in the middle, with the added jitter, my sample may be garbage.
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Online SiliconWizard

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Re: Modern equivalent of 74HC4046 PLL?
« Reply #13 on: May 09, 2020, 07:01:54 pm »
You don't need an edge "right in the middle". You just need to have some reasonable leeway.
 
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Online BrianHG

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Re: Modern equivalent of 74HC4046 PLL?
« Reply #14 on: July 12, 2020, 10:42:49 pm »
Ok, so I bought this chip MK9173-15 from Ebay, US seller, good communication, all seems legit  :blah:. It kind of works. I input ~15KHz and it outputs 21MHz. The jitter however is horrible but the LCD module doesn't seem to care.
Is this expected from a genlock chip like this or is it because I bought from Ebay?
For that degree of jitter, I would just use the 74HC4046 tuned to 10.5MHz.  Then in your FPGA, 2x that to the required 21MHz.  The clock would be much cleaner as you can tune your loop filter with the 74HC4046.  There are other modern PLL IC from TI which require a crystal/resonator which have a analog input tuning pin.  I made a video genlock using this chip where 100% inside the FPGA, I do the phase comparison and feed 2 outputs to charge and discharge that PLL analog vcxo input.  The resulting clock had no measurable jitter on my 5gsps 500Mhz Tektronix scope while a fixed 5v crystal oscillator had clearly visible jitter after 1/15000 of a second from trigger. (TI's CDCE913 1pll /CDCE925 2pll vcxo.  Tuning range is narrow for crystal at +/-150ppm, much more leeway for resonator, but the clock 60ps jitter performance is great and you have the option of 2 plls for other needs and a 160MHz range.)

Also for generating a clock from a 15Khz signal being a sync from a video source, divide that sync by 2 in the FPGA, giving you a 50/50 7.5KHz signal out to feed your 74HC4046 phase comparator.  It's phase locked loop lock capabilities are far superior when fed 50/50 duty cycles reference sources.  Also, in the FPGA, make sure you specify Fast input and Fast output registers in the assignments for the associated IOs when generating these phase reference timing outputs so that build-2-build, you will always get the same phase offset response down to an exact picosecond unless you alter the structure of the code involved with generating those signals.
« Last Edit: July 13, 2020, 12:51:23 am by BrianHG »
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Offline dmendesf

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Re: Modern equivalent of 74HC4046 PLL?
« Reply #15 on: July 12, 2020, 11:58:34 pm »
Seems you got spread spectrum for free...
 

Offline Miti

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Re: Modern equivalent of 74HC4046 PLL?
« Reply #16 on: July 13, 2020, 01:23:07 am »
Seems you got spread spectrum for free...

 :-DD Yes...
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Online BrianHG

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Re: Modern equivalent of 74HC4046 PLL?
« Reply #17 on: July 13, 2020, 02:35:18 am »
Ok, so I bought this chip MK9173-15 from Ebay, US seller, good communication, all seems legit  :blah:. It kind of works. I input ~15KHz and it outputs 21MHz. The jitter however is horrible but the LCD module doesn't seem to care.
Is this expected from a genlock chip like this or is it because I bought from Ebay?
Have you considered that the PLL has generated a clean clock and the H-Sync coming from your source has jitter in it?
You might be able to check this by locking onto 2 H-syncs and zooming into the second one on the right to the current timebase to see if there is any built up jitter.
You can also do this with the PLL chip.

Also, have you analog isolated the PLL chip from your digital side.  This includes using series resistors to feed the phase comparator inputs and clk output to decouple any high frequency leakage working it's way back into the PLL vco.
« Last Edit: July 13, 2020, 02:40:31 am by BrianHG »
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Offline Miti

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Re: Modern equivalent of 74HC4046 PLL?
« Reply #18 on: July 14, 2020, 12:23:40 am »
Have you considered that the PLL has generated a clean clock and the H-Sync coming from your source has jitter in it?
You might be able to check this by locking onto 2 H-syncs and zooming into the second one on the right to the current timebase to see if there is any built up jitter.
You can also do this with the PLL chip.

I did my first tests with the FY6600 signal generator and I think that contributed to the terrible jitter. I remembered then that the generator may be jittery on square wave and, sure enough, it was. Then I moved to the HP SA itself, no jitter there and the clock has improved a bit but it is still jittery. I don't have a screen shot of that.

Also, have you analog isolated the PLL chip from your digital side.  This includes using series resistors to feed the phase comparator inputs and clk output to decouple any high frequency leakage working it's way back into the PLL vco.

You mean adding some series resistors to the IN, FBIN and Clock outputs? What values?
« Last Edit: July 14, 2020, 12:29:53 am by Miti »
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Online BrianHG

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Re: Modern equivalent of 74HC4046 PLL?
« Reply #19 on: July 14, 2020, 02:09:36 am »
Have you considered that the PLL has generated a clean clock and the H-Sync coming from your source has jitter in it?
You might be able to check this by locking onto 2 H-syncs and zooming into the second one on the right to the current timebase to see if there is any built up jitter.
You can also do this with the PLL chip.

I did my first tests with the FY6600 signal generator and I think that contributed to the terrible jitter. I remembered then that the generator may be jittery on square wave and, sure enough, it was. Then I moved to the HP SA itself, no jitter there and the clock has improved a bit but it is still jittery. I don't have a screen shot of that.

Also, have you analog isolated the PLL chip from your digital side.  This includes using series resistors to feed the phase comparator inputs and clk output to decouple any high frequency leakage working it's way back into the PLL vco.

You mean adding some series resistors to the IN, FBIN and Clock outputs? What values?
100 ohm should do.
As for the supply, I would use a ferrite bead, of if the PLL is really low power, 10 to 100 ohm series with a 100nf and 10uf to GND.
Make sure you probe after the 100 ohm, not on the IC pin so that potential emi doesn't make it back into the pll.
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Online BrianHG

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Re: Modern equivalent of 74HC4046 PLL?
« Reply #20 on: July 19, 2020, 03:24:31 am »
I am curious.  If you are using an FPGA and you only need to sample pixels at 21MHz, or 10.5MHz, why bother with an external PLL?  In the FPGA, why not just operate the core, or video input at 210MHz, and software PLL select the appropriate 1 in approximate every 10 samples.  No funny low frequency sync clock regeneration.  Your end results will be finer than the jitter noise you are currently getting with external clock generation.

In fact, you can use 2 PLLs in the Cyclone, 1 from a reference crystal to generate an approximate 420 MHz (A clean chosen multiple of the H-Sync frequency + 1 clock cycle would work best), software synth a reference between 5 MHz to 10 MHz to feed a second PLL input, then use that one to generate a clean 21Mhz clock using the low-bandwidth mode to drive your LCD module.  Your overall jitter should be below 2ns.  Expect below 4ns jitter if you run the sync sampler at a more modest 210 MHz.
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Online Zero999

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Re: Modern equivalent of 74HC4046 PLL?
« Reply #21 on: July 19, 2020, 12:03:02 pm »
Why use an RC oscillator for 21MHz?

Use an LC oscillator instead. A VCO can be made by using a varactor diode for the capacitance, or part of it.
 

Online BrianHG

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Re: Modern equivalent of 74HC4046 PLL?
« Reply #22 on: July 19, 2020, 05:32:28 pm »
Yes, the old Amiga genlocks which generated the reference 28.63636MHz used an LC oscillator which was 1 transistor, 1 tuning diode, tuneable inductor & usually a 74HC04 to buffer the clock plus a bit of logic to drive the tuning voltage from the incoming Hsync and Amiga's Hsync output.  Vsync was driven back into the Amiga video port where the computer internally moved it's Vsync position.

No oscillator needed for his design since he is using it to capture so low resolution 2 bit color B&W image while having an FPGA with 4 plls in it which can run circles around a single pixel width with something like 10x oversampling.
« Last Edit: July 19, 2020, 05:46:40 pm by BrianHG »
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Offline Miti

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Re: Modern equivalent of 74HC4046 PLL?
« Reply #23 on: July 20, 2020, 10:43:49 am »
I am curious.  If you are using an FPGA and you only need to sample pixels at 21MHz, or 10.5MHz, why bother with an external PLL?  In the FPGA, why not just operate the core, or video input at 210MHz, and software PLL select the appropriate 1 in approximate every 10 samples.  No funny low frequency sync clock regeneration.  Your end results will be finer than the jitter noise you are currently getting with external clock generation.

In fact, you can use 2 PLLs in the Cyclone, 1 from a reference crystal to generate an approximate 420 MHz (A clean chosen multiple of the H-Sync frequency + 1 clock cycle would work best), software synth a reference between 5 MHz to 10 MHz to feed a second PLL input, then use that one to generate a clean 21Mhz clock using the low-bandwidth mode to drive your LCD module.  Your overall jitter should be below 2ns.  Expect below 4ns jitter if you run the sync sampler at a more modest 210 MHz.

Very interesting idea! The video clock is 10.5MHz divided from a 21MHz oscillator. The VGA clock is 55.125MHz. So I’ll have to generate something around 420MHz from a 25 or 50 MHz oscillator, then divide it down to about 10MHz while resetting the divider at the end of every line on the rising edge of the HSync, then feed this clock to another 2 PLLs to make 21MHz and 55.125MHz.
Did I get this right?
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Online BrianHG

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Re: Modern equivalent of 74HC4046 PLL?
« Reply #24 on: July 20, 2020, 01:53:00 pm »
Yes, really close, except 420MHz is overkill while 210MHz will do and since it is a short input counter section, you will not have any trouble with the FMAX on the slowest cyclone.  Even 420 might work, but this is not how you do this if you want an easy sample pixel clock source.  There are a few minor tricks to get a few controls and optional second PLL to get this to work the way you want.

Item #1, is the pixel sample clock actually 10.5MHz on the dot, or 21MHz on the dot?
Item #2, you need to know how many clock 10.5/21MHz cycles it is from H-Sync to H-Sync, not how many pixels are on the screen.  It is also important to know if this is an odd number.  I've writen the rest assuming it is an even number.

Next, if 21MHz is the right figure, choose a core clock frequency 16x this figure:
This means make 1 PLL in the cyclone 336MHz from your 25/50MHz source.

Make a sync UP counter with sync reset (not async) with 6 bits.

Next for the sync input.
First make that registered.
Then with a second clk delay register, make a falling edge transition detector which will be the reset for your counter.

Note that at stage 2 in developement, you will want to make this reset a selectable/programmable pipe delay of 1 to 32 clock cycles as this will adjust the sample phase of you pixel sampling period so you may grab pixels on the center sweet spot.

Next, make a registered output tied to bit 4 (starting at bit 0) of this counter.
This output will contain your new 10.5MHz clock.

If Your H-Sync pixel clock divides into 4, use bit 5 for a reference 5.25 MHz clock, otherwise you may need to switch to 10.5MHz on bit 4.

In Quartus, just tie bit 5, 5.25MHz into a second 1:4 PLL to generate a new system 21MHz with a 'low bandwidth' setting.
That 'low bandwidth' setting slows down the Cyclone's PLL phase alignment to below 1 MHz smoothing out that potential +/- 2ns glitch once every few H-Syncs.  That's your new pixel sampling clock.  (Make it a 1:2 if the true pixel sampling is only 10.5MHz)

If you have any HDL troubles, or some added features to remove H-Sync noise, or transfer sampled data between clock domains, make a new thread in the 'FPGA' section of this forum.  Note I can only really help with Verilog or System Verilog or Quartus block diagram entry.

Looking at you current scope PLL jitter snapshot, this solution directly outputting bit 3 or 4 of you counter should reveal a 10.5/21MHz clock with +/-1.5ns jitter around the H-sync if any at all.  Unless your scope crystal clock is junk, this should roast your current PLL scope shots.

Outputting the second PLL from the cyclone with the low bandwidth setting generated from that clock would have a smoothed out effect.

As for the screen you are driving.  There usually is enough play to operate it from a fairly clean multiple of the 10.5MHz clock, but, the cyclone's pll is quite capable of doing simultaneous fractional outputs from 1 PLL, so it can easily make the 55.125 along the filtered 10.5MHz or 21MHz clock, or even all 3 clocks.

« Last Edit: July 20, 2020, 03:01:13 pm by BrianHG »
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