Electronics > Projects, Designs, and Technical Stuff
Modern equivalent of 74HC4046 PLL?
Miti:
Ok, so I bought this chip MK9173-15 from Ebay, US seller, good communication, all seems legit :blah:. It kind of works. I input ~15KHz and it outputs 21MHz. The jitter however is horrible but the LCD module doesn't seem to care.
Is this expected from a genlock chip like this or is it because I bought from Ebay?
Zoli:
--- Quote from: Miti on May 08, 2020, 11:42:28 pm ---...
The jitter however is horrible but the LCD module doesn't seem to care.
...
--- End quote ---
Because you have a good "eye pattern"?
/ducks
I mean, the HF(21MHz) signal statistically is "cleanly" centered over the referece(15kHz) falling edge.
Of course, it would be nice to have a clean, jitterfree 21 MHZ, but I think, as long as the display doesn't care, why should you?
/hides
Miti:
--- Quote from: Zoli on May 09, 2020, 05:50:31 am ---Of course, it would be nice to have a clean, jitterfree 21 MHZ, but I think, as long as the display doesn't care, why should you?
--- End quote ---
Well, the input to this circuit is the video output of an HP8591E spectrum analyzer that I want to up-convert to 1024x768 VGA. I wonder how sampling would be affected by the jitter. I have 95ns to sample the pixel so if I don't have a clock right in the middle, with the added jitter, my sample may be garbage.
SiliconWizard:
You don't need an edge "right in the middle". You just need to have some reasonable leeway.
BrianHG:
--- Quote from: Miti on May 08, 2020, 11:42:28 pm ---Ok, so I bought this chip MK9173-15 from Ebay, US seller, good communication, all seems legit :blah:. It kind of works. I input ~15KHz and it outputs 21MHz. The jitter however is horrible but the LCD module doesn't seem to care.
Is this expected from a genlock chip like this or is it because I bought from Ebay?
--- End quote ---
For that degree of jitter, I would just use the 74HC4046 tuned to 10.5MHz. Then in your FPGA, 2x that to the required 21MHz. The clock would be much cleaner as you can tune your loop filter with the 74HC4046. There are other modern PLL IC from TI which require a crystal/resonator which have a analog input tuning pin. I made a video genlock using this chip where 100% inside the FPGA, I do the phase comparison and feed 2 outputs to charge and discharge that PLL analog vcxo input. The resulting clock had no measurable jitter on my 5gsps 500Mhz Tektronix scope while a fixed 5v crystal oscillator had clearly visible jitter after 1/15000 of a second from trigger. (TI's CDCE913 1pll /CDCE925 2pll vcxo. Tuning range is narrow for crystal at +/-150ppm, much more leeway for resonator, but the clock 60ps jitter performance is great and you have the option of 2 plls for other needs and a 160MHz range.)
Also for generating a clock from a 15Khz signal being a sync from a video source, divide that sync by 2 in the FPGA, giving you a 50/50 7.5KHz signal out to feed your 74HC4046 phase comparator. It's phase locked loop lock capabilities are far superior when fed 50/50 duty cycles reference sources. Also, in the FPGA, make sure you specify Fast input and Fast output registers in the assignments for the associated IOs when generating these phase reference timing outputs so that build-2-build, you will always get the same phase offset response down to an exact picosecond unless you alter the structure of the code involved with generating those signals.
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