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Modern equivalent of 74HC4046 PLL?

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dmendesf:
Seems you got spread spectrum for free...

Miti:

--- Quote from: dmendesf on July 12, 2020, 11:58:34 pm ---Seems you got spread spectrum for free...

--- End quote ---

 :-DD Yes...

BrianHG:

--- Quote from: Miti on May 08, 2020, 11:42:28 pm ---Ok, so I bought this chip MK9173-15 from Ebay, US seller, good communication, all seems legit  :blah:. It kind of works. I input ~15KHz and it outputs 21MHz. The jitter however is horrible but the LCD module doesn't seem to care.
Is this expected from a genlock chip like this or is it because I bought from Ebay?

--- End quote ---
Have you considered that the PLL has generated a clean clock and the H-Sync coming from your source has jitter in it?
You might be able to check this by locking onto 2 H-syncs and zooming into the second one on the right to the current timebase to see if there is any built up jitter.
You can also do this with the PLL chip.

Also, have you analog isolated the PLL chip from your digital side.  This includes using series resistors to feed the phase comparator inputs and clk output to decouple any high frequency leakage working it's way back into the PLL vco.

Miti:

--- Quote from: BrianHG on July 13, 2020, 02:35:18 am ---Have you considered that the PLL has generated a clean clock and the H-Sync coming from your source has jitter in it?
You might be able to check this by locking onto 2 H-syncs and zooming into the second one on the right to the current timebase to see if there is any built up jitter.
You can also do this with the PLL chip.

--- End quote ---

I did my first tests with the FY6600 signal generator and I think that contributed to the terrible jitter. I remembered then that the generator may be jittery on square wave and, sure enough, it was. Then I moved to the HP SA itself, no jitter there and the clock has improved a bit but it is still jittery. I don't have a screen shot of that.


--- Quote from: BrianHG on July 13, 2020, 02:35:18 am ---Also, have you analog isolated the PLL chip from your digital side.  This includes using series resistors to feed the phase comparator inputs and clk output to decouple any high frequency leakage working it's way back into the PLL vco.

--- End quote ---

You mean adding some series resistors to the IN, FBIN and Clock outputs? What values?

BrianHG:

--- Quote from: Miti on July 14, 2020, 12:23:40 am ---
--- Quote from: BrianHG on July 13, 2020, 02:35:18 am ---Have you considered that the PLL has generated a clean clock and the H-Sync coming from your source has jitter in it?
You might be able to check this by locking onto 2 H-syncs and zooming into the second one on the right to the current timebase to see if there is any built up jitter.
You can also do this with the PLL chip.

--- End quote ---

I did my first tests with the FY6600 signal generator and I think that contributed to the terrible jitter. I remembered then that the generator may be jittery on square wave and, sure enough, it was. Then I moved to the HP SA itself, no jitter there and the clock has improved a bit but it is still jittery. I don't have a screen shot of that.


--- Quote from: BrianHG on July 13, 2020, 02:35:18 am ---Also, have you analog isolated the PLL chip from your digital side.  This includes using series resistors to feed the phase comparator inputs and clk output to decouple any high frequency leakage working it's way back into the PLL vco.

--- End quote ---

You mean adding some series resistors to the IN, FBIN and Clock outputs? What values?

--- End quote ---
100 ohm should do.
As for the supply, I would use a ferrite bead, of if the PLL is really low power, 10 to 100 ohm series with a 100nf and 10uf to GND.
Make sure you probe after the 100 ohm, not on the IC pin so that potential emi doesn't make it back into the pll.

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