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Modern equivalent of 74HC4046 PLL?

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BrianHG:
You have got to be kidding me....
Ok, you will need to use 2 PLLs to get the 336MHz.
PLL #1 to switch from 25/50MHz to 21MHz.
PLL #2 to go from 21MHz to 336MHz.
Otherwise, you will end up with an odd clock frequency value of 336.11111MHz if you use 1 PLL.
Or, if you have a different reference oscillator which can divide cleanly into 336MHz like 27MHz, or 8MHz/16/24/32MHz, 54MHz, 13.5MHz ect...

If you have 3 PLLs in your Cyclone, this project will work fine with any oscillator you already have.
This changes is the sample clock is actually something slightly different like 10.4MHz or 10.6MHz.

Miti:

--- Quote from: BrianHG on July 19, 2020, 05:32:28 pm ---No oscillator needed for his design since he is using it to capture so low resolution 2 bit color B&W image while having an FPGA with 4 plls in it which can run circles around a single pixel width with something like 10x oversampling.

--- End quote ---

I’ll be using a Cyclone 4 in TQFP 144 package. It has two PLLs only.

Miti:

--- Quote from: BrianHG on July 20, 2020, 02:32:07 pm ---You have got to be kidding me....
Ok, you will need to use 2 PLLs to get the 336MHz.
PLL #1 to switch from 25/50MHz to 21MHz.
PLL #2 to go from 21MHz to 336MHz.
Otherwise, you will end up with an odd clock frequency value of 336.11111MHz if you use 1 PLL.
Or, if you have a different reference oscillator which can divide cleanly into 336MHz like 27MHz, or 8MHz/16/24/32MHz, 54MHz, 13.5MHz ect...

If you have 3 PLLs in your Cyclone, this project will work fine with any oscillator you already have.
This changes is the sample clock is actually something slightly different like 10.4MHz or 10.6MHz.

--- End quote ---

Don’t worry, I’ve checked, 24MHz would do it.

BrianHG:

--- Quote from: Miti on July 20, 2020, 06:52:11 pm ---
--- Quote from: BrianHG on July 20, 2020, 02:32:07 pm ---You have got to be kidding me....
Ok, you will need to use 2 PLLs to get the 336MHz.
PLL #1 to switch from 25/50MHz to 21MHz.
PLL #2 to go from 21MHz to 336MHz.
Otherwise, you will end up with an odd clock frequency value of 336.11111MHz if you use 1 PLL.
Or, if you have a different reference oscillator which can divide cleanly into 336MHz like 27MHz, or 8MHz/16/24/32MHz, 54MHz, 13.5MHz ect...

If you have 3 PLLs in your Cyclone, this project will work fine with any oscillator you already have.
This changes is the sample clock is actually something slightly different like 10.4MHz or 10.6MHz.

--- End quote ---

Don’t worry, I’ve checked, 24MHz would do it.

--- End quote ---
Yup, 24 MHz multiplies x 14 to perfectly make 336MHz.
2 PLLs will work fine.
Making a 6 bit counter run at 336MHz will also be not problem.
Since your 336MHz clock will either be ever so slightly slower or faster than the scope's H-sync generated from the 10.5MHz, your final total correction jitter will be an occasional 2.976ns skip in 1 direction.

     I haven't a clue, but if you can get a 6 bit counter running at 672MHz, this occasional corrective skip will be down at 1.488ns at a time.  Having a code configured fixed phase alignment setting wouldn't be a problem, but you most likely could not get a software controlled one operating at 672MHz unless it's a -6 Cyclone, or just something ingeniously designed.

     Clocking a second PLL from the top bit of the 6 bit counter with the low bandwidth loop filter will make that PLL slowly adjust it's rate to align to these skips filtering out any abrupt transition step.  That second PLL can simultaneously make you sample clock and video output clock.

     Though, if you have a little flexibility on that VGA clock, like running it at 52.5MHz and using a different horizontal sync, front, and back porch values, this figure squarely divides into selecting a single core clock of 105MHz.  Where you output the VGA every second clock and sample video every 5th or 10th clock.

BrianHG:
Oh, 1 thing... You will need to drive an output pin with the counter bit[5], then tie that pin to an input to drive the second PLL.  Quartus doesn't like an internal logic cell driving the clk input of a PLL.

Make sure you make assignments:
fast output register for the counter bit[5]
and
fast input register for the sync inputs and video data inputs.

This way, as long as you register the inputs to a PLL clock as well as registered output, each compile build you make will have identical phase timing.  Otherwise, after each build, depending where the fitter places the logic, your phase delay will drift due to internal routing of the FPGA fabric.

In my designs, I usually fast input & fast output register all IOs in my designs at the minor possible cost of reaching an FMAX.  The usual fix is just an additional pipe-lined clocked register.

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